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prjxray
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Add bit for standards that are stepdown. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-28 17:11:10 -08:00
parent a2d32d19a3
commit ac4accbd57
2 changed files with 8 additions and 1 deletions
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7
fuzzers/030-iob/generate.py
View File

@ -41,6 +41,9 @@ def drives_for_iostandard(iostandard):
return drives return drives
STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
def main(): def main():
print("Loading tags") print("Loading tags")
segmk = Segmaker("design.bits") segmk = Segmaker("design.bits")
@ -60,6 +63,10 @@ def main():
iostandard = verilog.unquote(d['IOSTANDARD']) iostandard = verilog.unquote(d['IOSTANDARD'])
stepdown = iostandard in STEPDOWN_IOSTANDARDS
segmk.add_tile_tag(
d['tile'], '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
if d['type'] is None: if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0) segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)

2
fuzzers/030-iob/process_rdb.py
View File

@ -38,7 +38,7 @@ def main():
iostandard_lines = [] iostandard_lines = []
with open(args.input_rdb) as f: with open(args.input_rdb) as f:
for l in f: for l in f:
if '.LVCMOS' in l or '.LVTTL' in l: if ('.LVCMOS' in l or '.LVTTL' in l) and 'IOB_' in l:
iostandard_lines.append(l) iostandard_lines.append(l)
else: else:
print(l.strip()) print(l.strip())