mirror of https://github.com/openXC7/prjxray.git
Run make format.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
816bf44156
commit
a2d32d19a3
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@ -10,7 +10,8 @@ All contributions should be sent as
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### License
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All code in the Project X-Ray repository is licensed under the very permissive
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All software (code, associated documentation, support files, etc) in the
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Project X-Ray repository are licensed under the very permissive
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[ISC Licence](COPYING). A copy can be found in the [`COPYING`](COPYING) file.
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All new contributions must also be released under this license.
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@ -19,6 +19,7 @@ from prjxray import verilog
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import json
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import generate
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def process_parts(parts):
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if parts[0] == 'INOUT':
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yield 'type', 'IOBUF_INTERMDISABLE'
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@ -39,6 +40,7 @@ def process_parts(parts):
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yield 'IOSTANDARDS', parts[0].split('_')
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yield 'DRIVES', parts[2].split('_')
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def create_sites_from_fasm(root):
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sites = {}
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@ -52,9 +54,9 @@ def create_sites_from_fasm(root):
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site = parts[1]
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if (tile, site) not in sites:
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sites[(tile, site)] = {
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'tile': tile,
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'site_key': site,
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}
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'tile': tile,
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'site_key': site,
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}
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for key, value in process_parts(parts[2:]):
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sites[(tile, site)][key] = value
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@ -80,7 +82,7 @@ def process_specimen(root):
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for p in params:
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tile = p['tile']
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site = p['site']
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site_y = int(site[site.find('Y')+1:]) % 2
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site_y = int(site[site.find('Y') + 1:]) % 2
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if generate.skip_broken_tiles(p):
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continue
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@ -94,20 +96,21 @@ def process_specimen(root):
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site_from_fasm = sites[(tile, site_key)]
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assert p['type'] == site_from_fasm['type'], (
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tile, site_key, p, site_from_fasm)
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tile, site_key, p, site_from_fasm)
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if p['type'] is None:
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continue
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assert p['PULLTYPE'] == site_from_fasm['PULLTYPE'], (
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tile, site_key, p, site_from_fasm)
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tile, site_key, p, site_from_fasm)
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assert verilog.unquote(p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], (
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assert verilog.unquote(
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p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], (
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tile, site_key, p, site_from_fasm)
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if p['type'] != 'IBUF':
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assert p['SLEW'] == site_from_fasm['SLEW'], (
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tile, site_key, p, site_from_fasm)
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tile, site_key, p, site_from_fasm)
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assert 'I{}'.format(p['DRIVE']) in site_from_fasm['DRIVES'], (
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tile, site_key, p, site_from_fasm)
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@ -121,5 +124,6 @@ def main():
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print('No errors found!')
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if __name__ == "__main__":
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main()
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@ -13,6 +13,7 @@ def bitfilter(frame, word):
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return True
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def mk_drive_opt(iostandard, drive):
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return '{}.DRIVE.I{}'.format(iostandard, drive)
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@ -28,6 +29,7 @@ def skip_broken_tiles(d):
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return False
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def drives_for_iostandard(iostandard):
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if iostandard in ['LVTTL', 'LVCMOS18']:
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drives = [4, 8, 12, 16, 24]
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@ -38,6 +40,7 @@ def drives_for_iostandard(iostandard):
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return drives
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def main():
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print("Loading tags")
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segmk = Segmaker("design.bits")
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@ -63,14 +66,18 @@ def main():
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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for drive in drives_for_iostandard(iostandard):
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segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 0)
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 0)
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elif d['type'] == 'IBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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for drive in drives_for_iostandard(iostandard):
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segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 1)
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 1)
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elif d['type'] == 'OBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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@ -78,9 +85,13 @@ def main():
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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for drive in drives_for_iostandard(iostandard):
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if drive == d['DRIVE']:
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segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 1)
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 1)
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else:
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segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 0)
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 0)
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elif d['type'] == 'IOBUF_INTERMDISABLE':
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segmk.add_site_tag(site, 'INOUT', 1)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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@ -88,14 +99,16 @@ def main():
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if d['type'] is not None:
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segmaker.add_site_group_zero(
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segmk, site, "PULLTYPE.", ("NONE", "KEEPER", "PULLDOWN", "PULLUP"),
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"PULLDOWN", verilog.unquote(d['PULLTYPE']))
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segmk, site, "PULLTYPE.",
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("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
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verilog.unquote(d['PULLTYPE']))
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if d['type'] == 'IBUF' or d['type'] is None:
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continue
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drive_opts = set()
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for opt in ("LVCMOS25","LVCMOS33", "LVCMOS18", "LVCMOS15", "LVCMOS12", 'LVTTL'):
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for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
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"LVCMOS12", 'LVTTL'):
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for drive_opt in ("4", "8", "12", "16", "24"):
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if drive_opt == "16" and opt == "LVCMOS12":
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continue
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@ -106,23 +119,24 @@ def main():
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drive_opts.add(mk_drive_opt(opt, drive_opt))
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segmaker.add_site_group_zero(
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segmk, site, '', drive_opts,
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mk_drive_opt('LVCMOS25', '12'),
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segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'),
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mk_drive_opt(iostandard, d['DRIVE']))
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segmaker.add_site_group_zero(
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segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST",
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verilog.unquote(d['SLEW']))
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if 'ibufdisable_wire' in d:
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segmk.add_site_tag(site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0')
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segmk.add_site_tag(
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site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0')
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if 'intermdisable_wire' in d:
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segmk.add_site_tag(site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0')
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segmk.add_site_tag(
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site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0')
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segmk.compile(bitfilter=bitfilter)
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segmk.write(allow_empty=True)
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if __name__ == "__main__":
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main()
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@ -9,13 +9,16 @@ There are couple cases that need to be handled here:
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"""
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import argparse
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def get_name(l):
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parts = l.strip().split(' ')
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return parts[0]
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def get_site(l):
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return get_name(l).split('.')[1]
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def parse_bits(l):
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parts = l.strip().split(' ')
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if parts[1] == '<0':
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@ -23,8 +26,11 @@ def parse_bits(l):
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else:
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return frozenset(parts[1:])
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def main():
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parser = argparse.ArgumentParser(description="Convert IOB rdb into good rdb.""")
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parser = argparse.ArgumentParser(
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description="Convert IOB rdb into good rdb."
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"")
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parser.add_argument('input_rdb')
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args = parser.parse_args()
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@ -38,9 +44,9 @@ def main():
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print(l.strip())
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common_in_bits = {
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'IOB_Y0': set(),
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'IOB_Y1': set(),
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}
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'IOB_Y0': set(),
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'IOB_Y1': set(),
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}
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for l in iostandard_lines:
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if 'IN_OUT_COMMON' in l:
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common_in_bits[get_site(l)] |= parse_bits(l)
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@ -53,7 +59,6 @@ def main():
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drives = {}
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in_use = {}
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for l in iostandard_lines:
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name = get_name(l)
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site = get_site(l)
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@ -76,7 +81,8 @@ def main():
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iostandard_in[in_bits].append((site, iostandard))
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if name.endswith('.OUT'):
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outs[(site, iostandard)] = parse_bits(l) | in_use[(site, iostandard)]
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outs[(site,
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iostandard)] = parse_bits(l) | in_use[(site, iostandard)]
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if '.DRIVE.' in name and '.IN_OUT_COMMON' not in name:
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drive = name.split('.')[-1]
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@ -96,8 +102,8 @@ def main():
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assert len(site) == 1, site
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site = site.pop()
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print('IOB33.{}.{}.IN'.format(site, '_'.join(standards)),
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' '.join(bits))
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print(
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'IOB33.{}.{}.IN'.format(site, '_'.join(standards)), ' '.join(bits))
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iodrives = {}
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@ -105,14 +111,14 @@ def main():
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for site, iostandard in drives:
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for drive in drives[(site, iostandard)]:
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combined_bits = drives[(site, iostandard)][drive] | outs[(site, iostandard)]
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combined_bits = drives[(site, iostandard)][drive] | outs[(
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site, iostandard)]
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if site not in common_bits:
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common_bits[site] = set(common_in_bits[site])
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common_bits[site] |= combined_bits
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if combined_bits not in iodrives:
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iodrives[combined_bits] = []
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@ -128,10 +134,10 @@ def main():
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neg_bits = set('!' + bit for bit in (common_bits[site] - bits))
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print('IOB33.{}.{}.DRIVE.{}'.format(
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site,
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'_'.join(sorted(set(standards))),
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'_'.join(sorted(set(drives)))), ' '.join(bits | neg_bits))
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print(
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'IOB33.{}.{}.DRIVE.{}'.format(
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site, '_'.join(sorted(set(standards))), '_'.join(
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sorted(set(drives)))), ' '.join(bits | neg_bits))
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if __name__ == "__main__":
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@ -26,6 +26,7 @@ def gen_sites():
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if site_type in ['IOB33S', 'IOB33M']:
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yield tile_name, site_name
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def write_params(params):
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pinstr = 'tile,site,pin,iostandard,drive,slew\n'
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for vals in params:
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@ -35,13 +36,17 @@ def write_params(params):
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def run():
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tile_types = ['IBUF', 'OBUF', 'IOBUF_INTERMDISABLE', None, None, None, None, None]
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tile_types = [
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'IBUF', 'OBUF', 'IOBUF_INTERMDISABLE', None, None, None, None, None
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]
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i_idx = 0
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o_idx = 0
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io_idx = 0
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iostandards = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL']
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iostandards = [
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'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
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]
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iostandard = random.choice(iostandards)
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if iostandard in ['LVTTL', 'LVCMOS18']:
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@ -96,18 +101,22 @@ def run():
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p['owire'] = luts.get_next_input_net()
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p['DRIVE'] = random.choice(drives)
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p['SLEW'] = verilog.quote(random.choice(slews))
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p['tristate_wire'] = random.choice(('0', luts.get_next_output_net()))
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p['ibufdisable_wire'] = random.choice(('0', luts.get_next_output_net()))
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p['intermdisable_wire'] = random.choice(('0', luts.get_next_output_net()))
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p['tristate_wire'] = random.choice(
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('0', luts.get_next_output_net()))
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p['ibufdisable_wire'] = random.choice(
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('0', luts.get_next_output_net()))
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p['intermdisable_wire'] = random.choice(
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('0', luts.get_next_output_net()))
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io_idx += 1
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params.append(p)
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if p['type'] is not None:
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tile_params.append((tile, site, p['pad_wire'], iostandard,
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p['DRIVE'],
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verilog.unquote(p['SLEW']) if p['SLEW'] else None,
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verilog.unquote(p['PULLTYPE'])))
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tile_params.append(
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(
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tile, site, p['pad_wire'], iostandard, p['DRIVE'],
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verilog.unquote(p['SLEW']) if p['SLEW'] else None,
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verilog.unquote(p['PULLTYPE'])))
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write_params(tile_params)
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@ -120,10 +129,7 @@ def run():
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module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio);
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(* KEEP, DONT_TOUCH *)
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IDELAYCTRL();
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'''.format(
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n_di=i_idx,
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n_do=o_idx,
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n_dio=io_idx))
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'''.format(n_di=i_idx, n_do=o_idx, n_dio=io_idx))
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# Always output a LUT6 to make placer happy.
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print('''
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@ -145,13 +151,16 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
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) ibuf_{site} (
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.I({pad_wire}),
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.O({owire})
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);'''.format(**p), file=connects)
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);'''.format(**p),
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file=connects)
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if p['IDELAY_ONLY']:
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print("""
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print(
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"""
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(* KEEP, DONT_TOUCH *)
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IDELAYE2 idelay_site_{site} (
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.IDATAIN(idelay_{site})
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);""".format(**p), file=connects)
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);""".format(**p),
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file=connects)
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elif p['type'] == 'OBUF':
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print(
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@ -164,7 +173,8 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
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) ibuf_{site} (
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.O({pad_wire}),
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.I({iwire})
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);'''.format(**p), file=connects)
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);'''.format(**p),
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file=connects)
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elif p['type'] == 'IOBUF_INTERMDISABLE':
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print(
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'''
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@ -180,7 +190,8 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
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.T({tristate_wire}),
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.IBUFDISABLE({ibufdisable_wire}),
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.INTERMDISABLE({intermdisable_wire})
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);'''.format(**p), file=connects)
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);'''.format(**p),
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file=connects)
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for l in luts.create_wires_and_luts():
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print(l)
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@ -195,4 +206,3 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
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if __name__ == '__main__':
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run()
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|
|
@ -4,6 +4,7 @@ from prjxray.segmaker import Segmaker
|
|||
from prjxray import verilog
|
||||
import json
|
||||
|
||||
|
||||
def handle_data_width(segmk, d):
|
||||
if 'DATA_WIDTH' not in d:
|
||||
return
|
||||
|
|
@ -11,17 +12,21 @@ def handle_data_width(segmk, d):
|
|||
if d['DATA_RATE'] == 'DDR':
|
||||
return
|
||||
|
||||
for opt in [2, 3, 4,5, 6, 7, 8, 10, 14]:
|
||||
segmk.add_site_tag(d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt),
|
||||
d['DATA_WIDTH'] == opt)
|
||||
for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]:
|
||||
segmk.add_site_tag(
|
||||
d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt),
|
||||
d['DATA_WIDTH'] == opt)
|
||||
|
||||
|
||||
def handle_data_rate(segmk, d):
|
||||
if 'DATA_WIDTH' not in d:
|
||||
return
|
||||
|
||||
for opt in ['SDR', 'DDR']:
|
||||
segmk.add_site_tag(d['site'], 'ISERDES.DATA_RATE.{}'.format(opt),
|
||||
verilog.unquote(d['DATA_RATE']) == opt)
|
||||
segmk.add_site_tag(
|
||||
d['site'], 'ISERDES.DATA_RATE.{}'.format(opt),
|
||||
verilog.unquote(d['DATA_RATE']) == opt)
|
||||
|
||||
|
||||
def main():
|
||||
print("Loading tags")
|
||||
|
|
@ -43,9 +48,10 @@ def main():
|
|||
'MEMORY_QDR',
|
||||
'NETWORKING',
|
||||
'OVERSAMPLE',
|
||||
):
|
||||
segmk.add_site_tag(site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
|
||||
opt == verilog.unquote(d['INTERFACE_TYPE']))
|
||||
):
|
||||
segmk.add_site_tag(
|
||||
site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
|
||||
opt == verilog.unquote(d['INTERFACE_TYPE']))
|
||||
|
||||
if d['iddr_mux_config'] != 'none':
|
||||
segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1'])
|
||||
|
|
@ -54,52 +60,65 @@ def main():
|
|||
if 'INIT_Q3' in d:
|
||||
segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3'])
|
||||
segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])
|
||||
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1'])
|
||||
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2'])
|
||||
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3'])
|
||||
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4'])
|
||||
|
||||
if 'IS_CLK_INVERTED' in d:
|
||||
if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK',
|
||||
not d['IS_CLK_INVERTED'])
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLKB',
|
||||
not d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLKB', not d['IS_CLKB_INVERTED'])
|
||||
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK_XOR',
|
||||
d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK_NXOR',
|
||||
not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK_XOR',
|
||||
d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK_NXOR',
|
||||
not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
|
||||
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK_OR',
|
||||
d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK_NOR',
|
||||
not (d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']))
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK_AND',
|
||||
d['IS_CLK_INVERTED'] and d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_CLK_NAND',
|
||||
not (d['IS_CLK_INVERTED'] and d['IS_CLKB_INVERTED']))
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED']
|
||||
or d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK_NOR', not (
|
||||
d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']))
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED']
|
||||
and d['IS_CLKB_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_CLK_NAND', not (
|
||||
d['IS_CLK_INVERTED']
|
||||
and d['IS_CLKB_INVERTED']))
|
||||
|
||||
if 'IS_OCLK_INVERTED' in d:
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_OCLK',
|
||||
not d['IS_OCLK_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED'])
|
||||
|
||||
if 'IS_C_INVERTED' in d:
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_C',
|
||||
not d['IS_C_INVERTED'])
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.ZINV_C', not d['IS_C_INVERTED'])
|
||||
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_D',
|
||||
not d['IS_D_INVERTED'])
|
||||
segmk.add_site_tag(site, 'IFF.ZINV_D', not d['IS_D_INVERTED'])
|
||||
|
||||
if 'SRTYPE' in d:
|
||||
for opt in ['ASYNC', 'SYNC']:
|
||||
segmk.add_site_tag(site, 'IFF.SRTYPE.{}'.format(opt),
|
||||
verilog.unquote(d['SRTYPE']) == opt)
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.SRTYPE.{}'.format(opt),
|
||||
verilog.unquote(d['SRTYPE']) == opt)
|
||||
|
||||
if 'DDR_CLK_EDGE' in d:
|
||||
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE', 'SAME_EDGE_PIPELINED']:
|
||||
segmk.add_site_tag(site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
|
||||
verilog.unquote(d['DDR_CLK_EDGE']) == opt)
|
||||
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE',
|
||||
'SAME_EDGE_PIPELINED']:
|
||||
segmk.add_site_tag(
|
||||
site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
|
||||
verilog.unquote(d['DDR_CLK_EDGE']) == opt)
|
||||
|
||||
ofb_used = False
|
||||
if 'OFB_USED' in d and d['OFB_USED']:
|
||||
|
|
@ -163,9 +182,9 @@ def main():
|
|||
else:
|
||||
assert False, d['mux_config']
|
||||
|
||||
|
||||
segmk.compile()
|
||||
segmk.write(allow_empty=True)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ def gen_sites():
|
|||
if site_type in ['IOB33S', 'IOB33M']:
|
||||
yield tile_name, site_name
|
||||
|
||||
|
||||
def write_params(params):
|
||||
pinstr = 'tile,site,pin,iostandard,drive,slew\n'
|
||||
for vals in params:
|
||||
|
|
@ -33,13 +34,14 @@ def write_params(params):
|
|||
|
||||
open('params.csv', 'w').write(pinstr)
|
||||
|
||||
|
||||
def use_iserdese2(p, luts, connects):
|
||||
iobdelay = random.choice((
|
||||
'NONE',
|
||||
'BOTH',
|
||||
'IBUF',
|
||||
'IFD',
|
||||
))
|
||||
))
|
||||
|
||||
p['IOBDELAY'] = verilog.quote(iobdelay)
|
||||
p['INIT_Q1'] = random.randint(0, 1)
|
||||
|
|
@ -57,17 +59,19 @@ def use_iserdese2(p, luts, connects):
|
|||
p['IS_CLKB_INVERTED'] = random.randint(0, 1)
|
||||
p['IS_OCLK_INVERTED'] = random.randint(0, 1)
|
||||
p['IS_D_INVERTED'] = random.randint(0, 1)
|
||||
p['INTERFACE_TYPE'] = verilog.quote(random.choice((
|
||||
'MEMORY',
|
||||
'MEMORY_DDR3',
|
||||
'MEMORY_QDR',
|
||||
'NETWORKING',
|
||||
'OVERSAMPLE',
|
||||
)))
|
||||
p['INTERFACE_TYPE'] = verilog.quote(
|
||||
random.choice(
|
||||
(
|
||||
'MEMORY',
|
||||
'MEMORY_DDR3',
|
||||
'MEMORY_QDR',
|
||||
'NETWORKING',
|
||||
'OVERSAMPLE',
|
||||
)))
|
||||
p['DATA_RATE'] = verilog.quote(random.choice((
|
||||
'SDR',
|
||||
'DDR',
|
||||
)))
|
||||
)))
|
||||
if verilog.unquote(p['DATA_RATE']) == 'SDR':
|
||||
data_widths = [2, 3, 4, 5, 6, 7, 8]
|
||||
else:
|
||||
|
|
@ -96,7 +100,8 @@ def use_iserdese2(p, luts, connects):
|
|||
p['DYN_CLK_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE')))
|
||||
|
||||
if use_delay:
|
||||
print("""
|
||||
print(
|
||||
"""
|
||||
wire idelay_{site};
|
||||
|
||||
(* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *)
|
||||
|
|
@ -104,8 +109,8 @@ def use_iserdese2(p, luts, connects):
|
|||
) idelay_site_{site} (
|
||||
.IDATAIN({iwire}),
|
||||
.DATAOUT(idelay_{site})
|
||||
);""".format(
|
||||
**p), file=connects)
|
||||
);""".format(**p),
|
||||
file=connects)
|
||||
|
||||
p['ddly_connection'] = '.DDLY(idelay_{site}),'.format(**p)
|
||||
else:
|
||||
|
|
@ -115,7 +120,7 @@ def use_iserdese2(p, luts, connects):
|
|||
p['ODATA_RATE'] = verilog.quote(random.choice((
|
||||
'SDR',
|
||||
'DDR',
|
||||
)))
|
||||
)))
|
||||
if verilog.unquote(p['ODATA_RATE']) == 'SDR':
|
||||
data_widths = [2, 3, 4, 5, 6, 7, 8]
|
||||
else:
|
||||
|
|
@ -129,8 +134,8 @@ def use_iserdese2(p, luts, connects):
|
|||
else:
|
||||
p['TRISTATE_WIDTH'] = 4
|
||||
|
||||
|
||||
print("""
|
||||
print(
|
||||
"""
|
||||
wire tfb_{site};
|
||||
wire ofb_{site};
|
||||
|
||||
|
|
@ -149,8 +154,8 @@ def use_iserdese2(p, luts, connects):
|
|||
.OQ({owire}),
|
||||
.TQ({twire}),
|
||||
.OFB(ofb_{site})
|
||||
);""".format(
|
||||
**p), file=connects)
|
||||
);""".format(**p),
|
||||
file=connects)
|
||||
|
||||
p['ofb_connections'] = """
|
||||
.OFB(ofb_{site}),
|
||||
|
|
@ -158,8 +163,8 @@ def use_iserdese2(p, luts, connects):
|
|||
else:
|
||||
p['ofb_connections'] = ''
|
||||
|
||||
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *)
|
||||
ISERDESE2 #(
|
||||
.SERDES_MODE({SERDES_MODE}),
|
||||
|
|
@ -193,14 +198,15 @@ def use_iserdese2(p, luts, connects):
|
|||
.Q1({q1net}),
|
||||
.CLKDIV(0)
|
||||
);'''.format(
|
||||
clknet=luts.get_next_output_net(),
|
||||
clkbnet=luts.get_next_output_net(),
|
||||
oclknet=luts.get_next_output_net(),
|
||||
onet=luts.get_next_input_net(),
|
||||
q1net=luts.get_next_input_net(),
|
||||
shiftout1net=luts.get_next_input_net(),
|
||||
shiftout2net=luts.get_next_input_net(),
|
||||
**p), file=connects)
|
||||
clknet=luts.get_next_output_net(),
|
||||
clkbnet=luts.get_next_output_net(),
|
||||
oclknet=luts.get_next_output_net(),
|
||||
onet=luts.get_next_input_net(),
|
||||
q1net=luts.get_next_input_net(),
|
||||
shiftout1net=luts.get_next_input_net(),
|
||||
shiftout2net=luts.get_next_input_net(),
|
||||
**p),
|
||||
file=connects)
|
||||
|
||||
|
||||
def use_direct_and_iddr(p, luts, connects):
|
||||
|
|
@ -208,13 +214,13 @@ def use_direct_and_iddr(p, luts, connects):
|
|||
'direct',
|
||||
'idelay',
|
||||
'none',
|
||||
))
|
||||
))
|
||||
|
||||
p['iddr_mux_config'] = random.choice((
|
||||
'direct',
|
||||
'idelay',
|
||||
'none',
|
||||
))
|
||||
))
|
||||
|
||||
if p['iddr_mux_config'] != 'none':
|
||||
p['INIT_Q1'] = random.randint(0, 1)
|
||||
|
|
@ -222,13 +228,16 @@ def use_direct_and_iddr(p, luts, connects):
|
|||
p['IS_C_INVERTED'] = random.randint(0, 1)
|
||||
p['IS_D_INVERTED'] = random.randint(0, 1)
|
||||
p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
|
||||
p['DDR_CLK_EDGE'] = verilog.quote(random.choice((
|
||||
'OPPOSITE_EDGE',
|
||||
'SAME_EDGE',
|
||||
'SAME_EDGE_PIPELINED',
|
||||
)))
|
||||
p['DDR_CLK_EDGE'] = verilog.quote(
|
||||
random.choice(
|
||||
(
|
||||
'OPPOSITE_EDGE',
|
||||
'SAME_EDGE',
|
||||
'SAME_EDGE_PIPELINED',
|
||||
)))
|
||||
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *)
|
||||
IDDR #(
|
||||
.IS_D_INVERTED({IS_D_INVERTED}),
|
||||
|
|
@ -244,13 +253,16 @@ def use_direct_and_iddr(p, luts, connects):
|
|||
.Q2({q2})
|
||||
);
|
||||
'''.format(
|
||||
cnet=luts.get_next_output_net(),
|
||||
q1=luts.get_next_input_net(),
|
||||
q2=luts.get_next_input_net(),
|
||||
**p), file=connects)
|
||||
cnet=luts.get_next_output_net(),
|
||||
q1=luts.get_next_input_net(),
|
||||
q2=luts.get_next_input_net(),
|
||||
**p),
|
||||
file=connects)
|
||||
|
||||
if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p['iddr_mux_config'] == 'tristate_feedback':
|
||||
print("""
|
||||
if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p[
|
||||
'iddr_mux_config'] == 'tristate_feedback':
|
||||
print(
|
||||
"""
|
||||
wire idelay_{site};
|
||||
|
||||
(* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *)
|
||||
|
|
@ -258,56 +270,66 @@ def use_direct_and_iddr(p, luts, connects):
|
|||
) idelay_site_{site} (
|
||||
.IDATAIN({iwire}),
|
||||
.DATAOUT(idelay_{site})
|
||||
);""".format(
|
||||
**p), file=connects)
|
||||
);""".format(**p),
|
||||
file=connects)
|
||||
|
||||
print("""
|
||||
print(
|
||||
"""
|
||||
assign {owire} = {onet};
|
||||
assign {twire} = {tnet};
|
||||
""".format(
|
||||
onet=luts.get_next_output_net(),
|
||||
tnet=luts.get_next_output_net(),
|
||||
**p), file=connects)
|
||||
**p),
|
||||
file=connects)
|
||||
|
||||
if p['iddr_mux_config'] == 'direct':
|
||||
print('''
|
||||
assign iddr_d_{site} = {iwire};'''.format(
|
||||
**p,
|
||||
), file=connects)
|
||||
print(
|
||||
'''
|
||||
assign iddr_d_{site} = {iwire};'''.format(**p, ),
|
||||
file=connects)
|
||||
elif p['iddr_mux_config'] == 'idelay':
|
||||
print('''
|
||||
assign iddr_d_{site} = idelay_{site};'''.format(
|
||||
**p,
|
||||
), file=connects)
|
||||
print(
|
||||
'''
|
||||
assign iddr_d_{site} = idelay_{site};'''.format(**p, ),
|
||||
file=connects)
|
||||
elif p['iddr_mux_config'] == 'tristate_feedback':
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
assign iddr_d_{site} = tfb_{site} ? ofb_{site} : idelay_{site};'''.format(
|
||||
**p,
|
||||
), file=connects)
|
||||
**p, ),
|
||||
file=connects)
|
||||
elif p['iddr_mux_config'] == 'none':
|
||||
pass
|
||||
else:
|
||||
assert False, p['mux_config']
|
||||
|
||||
if p['mux_config'] == 'direct':
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
assign {net} = {iwire};'''.format(
|
||||
net=luts.get_next_input_net(),
|
||||
**p,
|
||||
), file=connects)
|
||||
net=luts.get_next_input_net(),
|
||||
**p,
|
||||
),
|
||||
file=connects)
|
||||
elif p['mux_config'] == 'idelay':
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
assign {net} = idelay_{site};'''.format(
|
||||
net=luts.get_next_input_net(),
|
||||
**p,
|
||||
), file=connects)
|
||||
net=luts.get_next_input_net(),
|
||||
**p,
|
||||
),
|
||||
file=connects)
|
||||
elif p['mux_config'] == 'none':
|
||||
pass
|
||||
else:
|
||||
assert False, p['mux_config']
|
||||
|
||||
|
||||
def run():
|
||||
iostandards = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL']
|
||||
iostandards = [
|
||||
'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
|
||||
]
|
||||
iostandard = random.choice(iostandards)
|
||||
|
||||
if iostandard in ['LVTTL', 'LVCMOS18']:
|
||||
|
|
@ -330,7 +352,6 @@ def run():
|
|||
if idx == 0:
|
||||
continue
|
||||
|
||||
|
||||
p = {}
|
||||
p['tile'] = tile
|
||||
p['site'] = site
|
||||
|
|
@ -342,16 +363,17 @@ def run():
|
|||
p['DRIVE'] = random.choice(drives)
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
|
||||
p['pad_wire'] = 'dio[{}]'.format(idx-1)
|
||||
p['owire'] = 'do_buf[{}]'.format(idx-1)
|
||||
p['iwire'] = 'di_buf[{}]'.format(idx-1)
|
||||
p['twire'] = 't[{}]'.format(idx-1)
|
||||
p['pad_wire'] = 'dio[{}]'.format(idx - 1)
|
||||
p['owire'] = 'do_buf[{}]'.format(idx - 1)
|
||||
p['iwire'] = 'di_buf[{}]'.format(idx - 1)
|
||||
p['twire'] = 't[{}]'.format(idx - 1)
|
||||
|
||||
params.append(p)
|
||||
tile_params.append((tile, site, p['pad_wire'], iostandard,
|
||||
p['DRIVE'],
|
||||
verilog.unquote(p['SLEW']) if p['SLEW'] else None,
|
||||
verilog.unquote(p['PULLTYPE'])))
|
||||
tile_params.append(
|
||||
(
|
||||
tile, site, p['pad_wire'], iostandard, p['DRIVE'],
|
||||
verilog.unquote(p['SLEW']) if p['SLEW'] else None,
|
||||
verilog.unquote(p['PULLTYPE'])))
|
||||
|
||||
write_params(tile_params)
|
||||
|
||||
|
|
@ -363,11 +385,11 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
|
|||
wire [`N_DI-1:0] di_buf;
|
||||
wire [`N_DI-1:0] do_buf;
|
||||
wire [`N_DI-1:0] t;
|
||||
'''.format(
|
||||
n_di=idx))
|
||||
'''.format(n_di=idx))
|
||||
|
||||
# Always output a LUT6 to make placer happy.
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy_lut();
|
||||
''')
|
||||
|
|
@ -375,7 +397,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
|
|||
any_idelay = False
|
||||
|
||||
for p in params:
|
||||
print('''
|
||||
print(
|
||||
'''
|
||||
wire iddr_d_{site};
|
||||
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
|
|
@ -387,8 +410,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
|
|||
.O({iwire}),
|
||||
.T({twire})
|
||||
);
|
||||
'''.format(
|
||||
**p), file=connects)
|
||||
'''.format(**p),
|
||||
file=connects)
|
||||
|
||||
p['use_iserdese2'] = random.randint(0, 1)
|
||||
if p['use_iserdese2']:
|
||||
|
|
@ -417,4 +440,3 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
|
|||
|
||||
if __name__ == '__main__':
|
||||
run()
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue