Add bit for standards that are stepdown.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/030-iob/generate.py

@@ -41,6 +41,9 @@ def drives_for_iostandard(iostandard):
     return drives
 
 
+STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
+
+
 def main():
     print("Loading tags")
     segmk = Segmaker("design.bits")
@@ -60,6 +63,10 @@ def main():
 
             iostandard = verilog.unquote(d['IOSTANDARD'])
 
+            stepdown = iostandard in STEPDOWN_IOSTANDARDS
+            segmk.add_tile_tag(
+                d['tile'], '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
+
             if d['type'] is None:
                 segmk.add_site_tag(site, 'INOUT', 0)
                 segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)

fuzzers/030-iob/process_rdb.py

@@ -38,7 +38,7 @@ def main():
     iostandard_lines = []
     with open(args.input_rdb) as f:
         for l in f:
-            if '.LVCMOS' in l or '.LVTTL' in l:
+            if ('.LVCMOS' in l or '.LVTTL' in l) and 'IOB_' in l:
                 iostandard_lines.append(l)
             else:
                 print(l.strip())