mirror of https://github.com/openXC7/prjxray.git
061-pcie-conf: rework pcie-conf fuzzer
Included changes: - unify params format to JSON - add generate_ports script - export attributes and ports to prjxray_db Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
This commit is contained in:
Jan Kowalewski
parent
0d9418a908
commit
ac25035fd4
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@ -5,23 +5,67 @@
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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SHELL = bash
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N ?= 40
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include ../fuzzer.mk
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BUILD_DIR = build_${XRAY_PART}
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database: build/segbits_pcie_bot.db
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SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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FUZDIR ?= ${PWD}
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CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
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build/segbits_pcie_bot.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_pcie_bot.rdb $(addsuffix /segdata_pcie_bot.txt,$(SPECIMENS))
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all: database
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build/segbits_pcie_bot.db: build/segbits_pcie_bot.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_pcie_bot.rdb \
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--seg-fn-out build/segbits_pcie_bot.db
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${XRAY_MASKMERGE} build/mask_pcie_bot.db $(addsuffix /segdata_pcie_bot.txt,$(SPECIMENS))
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$(SPECIMENS_OK): $(SPECIMENS_DEPS)
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mkdir -p ${BUILD_DIR}
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bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
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run:
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$(MAKE) clean
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$(MAKE) attrs
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$(MAKE) database
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$(MAKE) pushdb
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touch run.${XRAY_PART}.ok
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clean:
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rm -rf ${BUILD_DIR} run.${XRAY_PART}.ok
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.PHONY: all run clean
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attrs: $(FUZDIR)/attrs.json
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$(FUZDIR)/attrs.json: $(FUZDIR)/params.py
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python3 $(FUZDIR)/params.py --attrs-file $(FUZDIR)/attrs.json
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# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
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# as the index in the port bus
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SPECIAL_PINS = EDTCHANNELSIN1,EDTCHANNELSIN2,EDTCHANNELSIN3,EDTCHANNELSIN4,EDTCHANNELSIN5,EDTCHANNELSIN6,EDTCHANNELSIN7,EDTCHANNELSIN8,LL2SENDASREQL1,LL2SENDENTERL1,LL2SENDENTERL23,USERCLK2,EDTCHANNELSOUT1,EDTCHANNELSOUT2,EDTCHANNELSOUT3,EDTCHANNELSOUT4,EDTCHANNELSOUT5,EDTCHANNELSOUT6,EDTCHANNELSOUT7,EDTCHANNELSOUT8
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$(BUILD_DIR)/pcie_2_1_ports.csv: generate_ports.tcl
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env FILE_NAME=$(BUILD_DIR)/pcie_2_1_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
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$(BUILD_DIR)/pcie_2_1_ports.json: $(BUILD_DIR)/pcie_2_1_ports.csv
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python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/pcie_2_1_pins.csv $(BUILD_DIR)/pcie_2_1_ports.json --special-pins $(SPECIAL_PINS)
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database: $(BUILD_DIR)/segbits_pcie_bot.db $(BUILD_DIR)/pcie_2_1_ports.json
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$(BUILD_DIR)/segbits_pcie_bot.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o $(BUILD_DIR)/segbits_pcie_bot.rdb $(addsuffix /segdata_pcie_bot.txt,$(SPECIMENS))
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$(BUILD_DIR)/segbits_pcie_bot.db: $(BUILD_DIR)/segbits_pcie_bot.rdb
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${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
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--seg-fn-in $(BUILD_DIR)/segbits_pcie_bot.rdb \
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--seg-fn-out $(BUILD_DIR)/segbits_pcie_bot.db
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${XRAY_MASKMERGE} $(BUILD_DIR)/mask_pcie_bot.db $(addsuffix /segdata_pcie_bot.txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} pcie_bot build/segbits_pcie_bot.db
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${XRAY_MERGEDB} mask_pcie_bot build/mask_pcie_bot.db
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${XRAY_MERGEDB} pcie_bot $(BUILD_DIR)/segbits_pcie_bot.db
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${XRAY_MERGEDB} mask_pcie_bot $(BUILD_DIR)/mask_pcie_bot.db
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mkdir -p $(CELLS_DATA_DIR)
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cp $(FUZDIR)/attrs.json $(CELLS_DATA_DIR)/pcie_2_1_attrs.json
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cp $(BUILD_DIR)/pcie_2_1_ports.json $(CELLS_DATA_DIR)/pcie_2_1_ports.json
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.PHONY: database pushdb
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@ -10,9 +10,12 @@
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# SPDX-License-Identifier: ISC
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import json
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import os
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from prjxray.segmaker import Segmaker
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from params import boolean_params, hex_params, int_params
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BIN = "BIN"
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BOOL = "BOOL"
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def bitfilter(frame, bit):
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@ -26,26 +29,34 @@ def bitfilter(frame, bit):
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def main():
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segmk = Segmaker("design.bits")
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fuz_dir = os.getenv("FUZDIR", None)
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assert fuz_dir
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with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
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attrs = json.load(attr_file)
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print("Loading tags")
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with open('params.json') as f:
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params = json.load(f)
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site = params['site']
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for param, _ in boolean_params:
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for param, param_info in attrs.items():
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value = params[param]
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param_type = param_info["type"]
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param_digits = param_info["digits"]
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param_values = param_info["values"]
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segmk.add_site_tag(site, param, value)
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if param_type == BIN:
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bitstr = [
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int(x) for x in "{value:0{digits}b}".format(
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value=value, digits=param_digits)[::-1]
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]
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for param, digits in hex_params + int_params:
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value = int(params[param])
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bitstr = [
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int(x) for x in "{value:0{digits}b}".format(
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value=value, digits=digits)[::-1]
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]
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for i in range(digits):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
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for i in range(param_digits):
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segmk.add_site_tag(site, "%s[%u]" % (param, i), bitstr[i])
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else:
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assert param_type == BOOL
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segmk.add_site_tag(site, param, value == "TRUE")
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -0,0 +1,36 @@
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# Copyright (C) 2017-2021 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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proc dump_pins {file_name site_prefix} {
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set fp [open $file_name w]
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puts $fp "name,is_input,is_output"
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set site [lindex [get_sites $site_prefix*] 0]
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set pins [get_site_pins -of_objects $site]
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foreach pin $pins {
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set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
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if { $connected_pip == "" } {
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continue
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}
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set pin_name [lindex [split $pin "/"] 1]
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set is_input [get_property IS_INPUT $pin]
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set is_output [get_property IS_OUTPUT $pin]
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puts $fp "$pin_name,$is_input,$is_output"
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}
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close $fp
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}
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create_project -force -name design -part $::env(XRAY_PART)
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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dump_pins $::env(FILE_NAME) PCIE
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@ -9,6 +9,10 @@
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#
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# SPDX-License-Identifier: ISC
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import argparse
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import json
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from collections import OrderedDict
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boolean_params = [
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("AER_CAP_ECRC_CHECK_CAPABLE", 1),
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("AER_CAP_ECRC_GEN_CAPABLE", 1),
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@ -300,3 +304,37 @@ int_params = [
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("SPARE_BIT7", 1),
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("SPARE_BIT8", 1),
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]
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def dump_json():
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parser = argparse.ArgumentParser()
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parser.add_argument("--attrs-file", help="JSON output path", required=True)
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args = parser.parse_args()
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data = OrderedDict()
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# Prepare BOOL type attributes
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for param in boolean_params:
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data[param[0]] = {
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"type": "BOOL",
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"values": ["FALSE", "TRUE"],
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"digits": param[1]
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}
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# Prepare BIN type attributes
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for param in (hex_params + int_params):
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data[param[0]] = {
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"type": "BIN",
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"values": [(1 << param[1]) - 1],
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"digits": param[1]
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}
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data = dict(sorted(data.items()))
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# Emit JSON
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with open(args.attrs_file, "w") as f:
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json.dump(data, f, indent=4)
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if __name__ == "__main__":
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dump_json()
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@ -16,7 +16,9 @@ random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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from params import boolean_params, hex_params, int_params
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BIN = "BIN"
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BOOL = "BOOL"
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def gen_sites():
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@ -50,35 +52,33 @@ module top();
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verilog_attr = "#("
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# Add boolean parameters
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for param, _ in boolean_params:
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value = random.randint(0, 1)
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value_string = "TRUE" if value else "FALSE"
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fuz_dir = os.getenv("FUZDIR", None)
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assert fuz_dir
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with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
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attrs = json.load(attrs_file)
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for param, param_info in attrs.items():
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param_type = param_info["type"]
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param_values = param_info["values"]
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param_digits = param_info["digits"]
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if param_type == BOOL:
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value = random.choice(param_values)
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value_str = verilog.quote(value)
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elif param_type == BIN:
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if type(param_values) is int:
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value = param_values
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elif type(param_values) is list:
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if len(param_values) > 1:
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value = random.choice(param_values)
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else:
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value = random.randint(0, param_values[0])
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value_str = "{digits}'b{value:0{digits}b}".format(
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value=value, digits=param_digits)
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params[param] = value
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verilog_attr += """
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.{}({}),""".format(param, verilog.quote(value_string))
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# Add hexadecimal parameters
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for param, digits in hex_params:
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value = random.randint(0, 2**digits)
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params[param] = value
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verilog_attr += """
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.{}({}),""".format(
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param, "{digits}'h{value:08x}".format(value=value, digits=digits))
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# Add integer parameters
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for param, digits in int_params:
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value = random.randint(0, 2**digits)
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params[param] = value
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verilog_attr += """
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.{}({}),""".format(
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param, "{digits}'d{value:04d}".format(value=value, digits=digits))
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.{}({}),""".format(param, value_str)
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verilog_attr = verilog_attr.rstrip(",")
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verilog_attr += "\n)"
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