mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1614 from antmicro/add-gtp-ports-attrs-file
gtp: generate attributes and ports files to add to the db
This commit is contained in:
litghost
GitHub
commit
0d9418a908
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@ -0,0 +1,82 @@
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===============
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cell data files
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===============
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The *cell data* files are meant for specific primitives which have a common attribute format. The data contained in these files is generated/copied from the corresponding primitives' fuzzers.
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Naming convention
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-----------------
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The naming scheme for the cell data files is the following::
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<primitive_name>_<data_file_type>.json
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Example files:
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- ``gtpe2_common_attrs.json``
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- ``gtpe2_channel_ports.json``
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File format
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-----------
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There are two main data file types:
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- *Ports*
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- *Attributes*
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Attributes files
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~~~~~~~~~~~~~~~~
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This is a JSON file containing a dictionary of parameters, each one with, at most, four attributes:
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- Type: one of BIN, INT, STR, BOOL.
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- Values: all possible values that this parameter can assume. In case of `BIN` types, the values list contains only the maximum value reachable.
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- Digits: number of digits (or bits) required to enable a parameter.
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- Encoding: This is present only for `INT` types of parameters. These reflect the actual encoding of the parameter value in the bit array.
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As an example of parameter please, refer to the following::
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{
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"PLL0_REFCLK_DIV": {
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"type": "INT",
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"values": [1, 2],
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"encoding": [16, 0],
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"digits": 5
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},
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"RXLPMRESET_TIME": {
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"type": "BIN",
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"values": [127],
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"digits": 7
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},
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"RX_XCLK_SEL": {
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"type": "STR",
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"values": ["RXREC", "RXUSR"],
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"digits": 1
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},
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"TX_LOOPBACK_DRIVE_HIZ": {
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"type": "BOOL",
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"values": ["FALSE", "TRUE"],
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"digits": 1
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},
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}
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Ports files
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~~~~~~~~~~~
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This is a JSON file containing a dictionary of ports, each one with two attributes:
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- Direction: Corresponds to the port directiona and can have the ``input`` or ``output`` values.
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- Width: Indicates the width of the port bus.
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As an example of parameter please, refer to the following::
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{
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"CFGRESET": {
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"direction": "input",
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"width": 1
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},
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"CLKRSVD0": {
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"direction": "input",
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"width": 1
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}
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}
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@ -13,3 +13,4 @@ that are common for all Xilinx series 7 chip architectures.
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tile_type
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ppips
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mask
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cell_data
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@ -16,6 +16,7 @@ SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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FUZDIR ?= ${PWD}
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CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
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all: database
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@ -36,7 +37,17 @@ clean:
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.PHONY: all run clean
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database: ${BUILD_DIR}/segbits_gtp_common.db
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# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
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# as the index in the port bus
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SPECIAL_PINS = PLLRSVD1,PLLRSVD2,GTREFCLK0,GTREFCLK1,GTGREFCLK0,GTGREFCLK1,GTEASTREFCLK0,GTEASTREFCLK1,GTWESTREFCLK0,GTWESTREFCLK1,REFCLKOUTMONITOR0,REFCLKOUTMONITOR1
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$(BUILD_DIR)/gtpe2_common_ports.csv: generate_ports.tcl
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env FILE_NAME=$(BUILD_DIR)/gtpe2_common_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
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$(BUILD_DIR)/gtpe2_common_ports.json: $(BUILD_DIR)/gtpe2_common_ports.csv
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python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtpe2_common_pins.csv $(BUILD_DIR)/gtpe2_common_ports.json --special-pins $(SPECIAL_PINS)
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database: ${BUILD_DIR}/segbits_gtp_common.db $(BUILD_DIR)/gtpe2_common_ports.json
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${BUILD_DIR}/segbits_gtp_common.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o ${BUILD_DIR}/segbits_gtp_common.rdb $$(find $(SPECIMENS) -name "segdata_gtp_common*")
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@ -48,6 +59,9 @@ ${BUILD_DIR}/segbits_gtp_common.db: ${BUILD_DIR}/segbits_gtp_common.rdb
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${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtp_common.db $$(find $(SPECIMENS) -name "segdata_gtp_common*")
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pushdb:
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mkdir -p $(CELLS_DATA_DIR)
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cp attrs.json $(CELLS_DATA_DIR)/gtpe2_common_attrs.json
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cp $(BUILD_DIR)/gtpe2_common_ports.json $(CELLS_DATA_DIR)/gtpe2_common_ports.json
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BUILD_DIR=$(BUILD_DIR) source pushdb.sh
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.PHONY: database pushdb
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@ -62,6 +62,8 @@ def main():
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tile_type = params_dict["tile_type"]
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params_list = params_dict["params"]
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sites_in_tile = dict()
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for params in params_list:
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site = params["site"]
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tile = params["tile"]
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@ -69,6 +71,8 @@ def main():
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if "GTPE2_COMMON" not in site:
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continue
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sites_in_tile[tile] = site
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in_use = params["IN_USE"]
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segmk.add_site_tag(site, "IN_USE", in_use)
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@ -109,7 +113,7 @@ def main():
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"BOTH_GTREFCLK_USED"]:
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segmk.add_site_tag(site, param, params[param])
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segmk.add_tile_tag(tile, "ENABLE_DRP", params["ENABLE_DRP"])
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segmk.add_site_tag(site, "ENABLE_DRP", params["ENABLE_DRP"])
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for params in params_list:
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site = params["site"]
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@ -132,9 +136,11 @@ def main():
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value=params["CLKSWING_CFG"], digits=2)[::-1]
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]
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gtp_common_site = sites_in_tile[tile]
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for i in range(2):
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segmk.add_tile_tag(
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tile, "IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i), bitstr[i])
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segmk.add_site_tag(
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gtp_common_site, "IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i),
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bitstr[i])
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if tile_type.startswith("GTP_COMMON_MID"):
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bitfilter = bitfilter_gtp_common_mid
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@ -0,0 +1,36 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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proc dump_pins {file_name site_prefix} {
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set fp [open $file_name w]
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puts $fp "name,is_input,is_output"
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set site [lindex [get_sites $site_prefix*] 0]
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set pins [get_site_pins -of_objects $site]
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foreach pin $pins {
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set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
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if { $connected_pip == "" } {
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continue
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}
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set pin_name [lindex [split $pin "/"] 1]
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set is_input [get_property IS_INPUT $pin]
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set is_output [get_property IS_OUTPUT $pin]
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puts $fp "$pin_name,$is_input,$is_output"
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}
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close $fp
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}
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create_project -force -name design -part $::env(XRAY_PART)
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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dump_pins $::env(FILE_NAME) GTPE2_COMMON
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@ -16,6 +16,7 @@ SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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FUZDIR ?= ${PWD}
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CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
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all: database
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@ -34,7 +35,17 @@ clean:
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.PHONY: all run clean
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database: ${BUILD_DIR}/segbits_gtp_channelx.db
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# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
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# as the index in the port bus
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SPECIAL_PINS = CLKRSVD0,CLKRSVD1,GTREFCLK0,GTREFCLK1,GTNORTHREFCLK0,GTNORTHREFCLK1,GTSOUTHREFCLK0,GTSOUTHREFCLK1,RXUSRCLK,RXUSRCLK2,TXUSRCLK,TXUSRCLK2,RXOSINTID0,PMARSVDIN0,PMARSVDIN1,PMARSVDIN2,PMARSVDIN3,PMARSVDIN4,PMARSVDOUT0,PMARSVDOUT1
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$(BUILD_DIR)/gtpe2_channel_ports.csv:
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env FILE_NAME=$(BUILD_DIR)/gtpe2_channel_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
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$(BUILD_DIR)/gtpe2_channel_ports.json: $(BUILD_DIR)/gtpe2_channel_ports.csv
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python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtpe2_channel_pins.csv $(BUILD_DIR)/gtpe2_channel_ports.json --special-pins $(SPECIAL_PINS)
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database: ${BUILD_DIR}/segbits_gtp_channelx.db $(BUILD_DIR)/gtpe2_channel_ports.json
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${BUILD_DIR}/segbits_gtp_channelx.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 9 -o ${BUILD_DIR}/segbits_gtp_channelx.rdb $$(find $(SPECIMENS) -name "segdata_gtp_channel_[0123]*")
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@ -46,6 +57,9 @@ ${BUILD_DIR}/segbits_gtp_channelx.db: ${BUILD_DIR}/segbits_gtp_channelx.rdb
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${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtp_channelx.db $$(find $(SPECIMENS) -name "segdata_gtp_channel_[0123]*")
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pushdb:
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mkdir -p $(CELLS_DATA_DIR)
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cp attrs.json $(CELLS_DATA_DIR)/gtpe2_channel_attrs.json
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cp $(BUILD_DIR)/gtpe2_channel_ports.json $(CELLS_DATA_DIR)/gtpe2_channel_ports.json
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BUILD_DIR=$(BUILD_DIR) source pushdb.sh
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.PHONY: database pushdb
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@ -0,0 +1,36 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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proc dump_pins {file_name site_prefix} {
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set fp [open $file_name w]
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puts $fp "name,is_input,is_output"
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set site [lindex [get_sites $site_prefix*] 0]
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set pins [get_site_pins -of_objects $site]
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foreach pin $pins {
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set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
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if { $connected_pip == "" } {
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continue
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}
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set pin_name [lindex [split $pin "/"] 1]
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set is_input [get_property IS_INPUT $pin]
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set is_output [get_property IS_OUTPUT $pin]
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puts $fp "$pin_name,$is_input,$is_output"
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}
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close $fp
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}
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create_project -force -name design -part $::env(XRAY_PART)
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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dump_pins $::env(FILE_NAME) GTPE2_CHANNEL
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@ -0,0 +1,108 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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"""
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This script loads the pin dump of the desired BEL from Vivado and groups pins into ports.
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Ports that are not connected to the PL are not included. These ports are usually test and
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debug related ports, which are not useful from a P&R perspective.
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Ports are then written to a JSON file.
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"""
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import argparse
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import csv
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import json
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import re
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from collections import defaultdict
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def main():
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BUS_REGEX = re.compile("(.*[A-Z_])([0-9]+)$")
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# Parse arguments
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parser = argparse.ArgumentParser(
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description=__doc__,
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formatter_class=argparse.RawDescriptionHelpFormatter)
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parser.add_argument("csv", type=str, help="BEL pin dump file")
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parser.add_argument(
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"json",
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type=str,
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help="Output JSON file with BEL pins grouped into ports")
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parser.add_argument(
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"--special-pins",
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default="",
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type=str,
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required=False,
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help="Some pins cannot be decoded with the regex")
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args = parser.parse_args()
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# Load pin dump
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with open(args.csv, "r") as fp:
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pin_dump = list(csv.DictReader(fp))
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# Group pins into ports
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ports = defaultdict(lambda: {"direction": None, "width": 0})
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special_pins = args.special_pins.split(",")
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for pin in list(pin_dump):
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pin_name = pin["name"]
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name = None
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if pin_name in special_pins:
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# Full match
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name = pin_name
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else:
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# Partial match
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for special_pin in special_pins:
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if pin_name.startswith(special_pin):
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name = special_pin
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break
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if name is None:
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match = BUS_REGEX.match(pin_name)
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if match:
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name = match.group(1)
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else:
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name = pin_name
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# Get direction
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is_input = int(pin["is_input"])
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is_output = int(pin["is_output"])
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if is_input:
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direction = "input"
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elif is_output:
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direction = "output"
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else:
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assert False, pin
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# Add to port
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port = ports[name]
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if port["direction"] is None:
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port["direction"] = direction
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else:
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assert port["direction"] == direction, (port, direction, name)
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port["width"] += 1
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# Write pin ports to a JSON file
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with open(args.json, "w") as fp:
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json.dump(ports, fp, indent=1, sort_keys=True)
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if __name__ == "__main__":
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main()
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