mirror of https://github.com/openXC7/prjxray.git
bram config: basic working on Y1 but not Y0
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
fda33dd39e
commit
a58b2fefb4
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@ -13,24 +13,23 @@ f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_RAMB36E1'
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assert j['module'] == 'my_RAMB18E1'
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site = verilog.unquote(ps['LOC'])
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#print('site', site)
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# all of these bits are inverted
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ks = [
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'IS_CLKARDCLK_INVERTED',
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'IS_CLKBWRCLK_INVERTED',
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'IS_ENARDEN_INVERTED',
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'IS_ENBWREN_INVERTED',
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'IS_RSTRAMARSTRAM_INVERTED',
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'IS_RSTRAMB_INVERTED',
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'IS_RSTREGARSTREG_INVERTED',
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'IS_RSTREGB_INVERTED',
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('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
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('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
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('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
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('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
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('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
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('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
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('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
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('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
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]
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# FIXME
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#ks = ['IS_ENARDEN_INVERTED']
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for k in ks:
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segmk.add_site_tag(site, k, verilog.parsei(ps[k]))
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for param, tagname in ks:
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segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
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segmk.compile()
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segmk.write()
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@ -8,14 +8,20 @@ import json
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def gen_bram18():
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# yield "RAMB18_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMB18E1']):
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'''
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sample:
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"sites": {
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"RAMB18_X0Y50": "FIFO18E1",
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"RAMB18_X0Y51": "RAMB18E1",
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"RAMB36_X0Y25": "RAMBFIFO36E1"
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},
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'''
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for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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['RAMB18E1', 'FIFO18E1'])):
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yield site_name
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def gen_bram36():
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#yield "RAMB36_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMBFIFO36E1']):
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yield site_name
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@ -30,8 +36,12 @@ def gen_brams():
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#return
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#for _tile_name, site_name, _site_type in util.get_roi().gen_tiles():
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for site in gen_bram36():
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yield ('RAMBFIFO36E1', site)
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#for site in gen_bram36():
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# yield ('RAMBFIFO36E1', site)
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for site in gen_bram18():
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yield ('RAMB18E1', site)
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brams = list(gen_brams())
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@ -58,7 +68,26 @@ def vrandbit():
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for loci, (site_type, site) in enumerate(brams):
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def place_bram18():
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assert 0, 'FIXME'
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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params = {
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'LOC': verilog.quote(site),
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'IS_CLKARDCLK_INVERTED': vrandbit(),
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'IS_CLKBWRCLK_INVERTED': vrandbit(),
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'IS_ENARDEN_INVERTED': vrandbit(),
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'IS_ENBWREN_INVERTED': vrandbit(),
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'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
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'IS_RSTRAMB_INVERTED': vrandbit(),
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'IS_RSTREGARSTREG_INVERTED': vrandbit(),
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'IS_RSTREGB_INVERTED': vrandbit(),
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'RAM_MODE': '"TDP"',
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'WRITE_MODE_A': '"WRITE_FIRST"',
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'WRITE_MODE_B': '"WRITE_FIRST"',
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}
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return ('my_RAMB18E1', ports, params)
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def place_bram36():
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ports = {
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@ -80,24 +109,6 @@ for loci, (site_type, site) in enumerate(brams):
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'WRITE_MODE_A': '"WRITE_FIRST"',
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'WRITE_MODE_B': '"WRITE_FIRST"',
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}
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if 0:
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# FIXME
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params = {
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'LOC': verilog.quote(site),
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'IS_CLKARDCLK_INVERTED': "1'b0",
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'IS_CLKBWRCLK_INVERTED': "1'b0",
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#'IS_ENARDEN_INVERTED': vrandbit(),
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'IS_ENARDEN_INVERTED':
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("1'b" + str(int(os.getenv("SEEDN")) - 1)),
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'IS_ENBWREN_INVERTED': "1'b0",
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'IS_RSTRAMARSTRAM_INVERTED': "1'b0",
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'IS_RSTRAMB_INVERTED': "1'b0",
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'IS_RSTREGARSTREG_INVERTED': "1'b0",
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'IS_RSTREGB_INVERTED': "1'b0",
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'RAM_MODE': '"TDP"',
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'WRITE_MODE_A': '"WRITE_FIRST"',
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'WRITE_MODE_B': '"WRITE_FIRST"',
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}
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return ('my_RAMB36E1', ports, params)
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modname, ports, params = {
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@ -202,8 +213,7 @@ print(
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.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
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.RAM_MODE(RAM_MODE),
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.WRITE_MODE_A(WRITE_MODE_A),
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.WRITE_MODE_B(WRITE_MODE_B),
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.SIM_DEVICE("VIRTEX6")
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.WRITE_MODE_B(WRITE_MODE_B)
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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@ -270,8 +280,7 @@ print(
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.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
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.RAM_MODE(RAM_MODE),
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.WRITE_MODE_A(WRITE_MODE_A),
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.WRITE_MODE_B(WRITE_MODE_B),
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.SIM_DEVICE("VIRTEX6")
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.WRITE_MODE_B(WRITE_MODE_B)
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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@ -228,6 +228,15 @@ class Segmaker:
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else:
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assert 0
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def name_bram18():
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# RAMB18_X0Y41
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if re.match(r"RAMB18_X.*Y[0-9]*[02468]", site):
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return "RAMB18_Y0"
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elif re.match(r"RAMB18_X.*Y[0-9]*[13579]", site):
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return "RAMB18_Y1"
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else:
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assert 0
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def name_default():
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# most sites are unique within their tile
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# TODO: maybe verify against DB?
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@ -235,6 +244,7 @@ class Segmaker:
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sitekey = {
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'SLICE': name_slice,
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'RAMB18': name_bram18,
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}.get(site_prefix, name_default)()
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for name, value in self.site_tags[site].items():
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