From a58b2fefb40a6441d85584a74ec8006128721e54 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Wed, 24 Oct 2018 10:47:56 -0700 Subject: [PATCH] bram config: basic working on Y1 but not Y0 Signed-off-by: John McMaster --- fuzzers/101-bram-config/generate.py | 27 ++++++------ fuzzers/101-bram-config/top.py | 67 ++++++++++++++++------------- prjxray/segmaker.py | 10 +++++ 3 files changed, 61 insertions(+), 43 deletions(-) diff --git a/fuzzers/101-bram-config/generate.py b/fuzzers/101-bram-config/generate.py index c10ae715..9af9b949 100644 --- a/fuzzers/101-bram-config/generate.py +++ b/fuzzers/101-bram-config/generate.py @@ -13,24 +13,23 @@ f.readline() for l in f: j = json.loads(l) ps = j['params'] - assert j['module'] == 'my_RAMB36E1' + assert j['module'] == 'my_RAMB18E1' site = verilog.unquote(ps['LOC']) + #print('site', site) + # all of these bits are inverted ks = [ - 'IS_CLKARDCLK_INVERTED', - 'IS_CLKBWRCLK_INVERTED', - 'IS_ENARDEN_INVERTED', - 'IS_ENBWREN_INVERTED', - 'IS_RSTRAMARSTRAM_INVERTED', - 'IS_RSTRAMB_INVERTED', - 'IS_RSTREGARSTREG_INVERTED', - 'IS_RSTREGB_INVERTED', + ('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'), + ('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'), + ('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'), + ('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'), + ('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'), + ('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'), + ('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'), + ('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'), ] - # FIXME - #ks = ['IS_ENARDEN_INVERTED'] - - for k in ks: - segmk.add_site_tag(site, k, verilog.parsei(ps[k])) + for param, tagname in ks: + segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param])) segmk.compile() segmk.write() diff --git a/fuzzers/101-bram-config/top.py b/fuzzers/101-bram-config/top.py index 3f503e2e..8566bd7d 100644 --- a/fuzzers/101-bram-config/top.py +++ b/fuzzers/101-bram-config/top.py @@ -8,14 +8,20 @@ import json def gen_bram18(): - # yield "RAMB18_X%dY%d" % (x, y) - for _tile_name, site_name, _site_type in util.get_roi().gen_sites( - ['RAMB18E1']): + ''' + sample: + "sites": { + "RAMB18_X0Y50": "FIFO18E1", + "RAMB18_X0Y51": "RAMB18E1", + "RAMB36_X0Y25": "RAMBFIFO36E1" + }, + ''' + for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites( + ['RAMB18E1', 'FIFO18E1'])): yield site_name def gen_bram36(): - #yield "RAMB36_X%dY%d" % (x, y) for _tile_name, site_name, _site_type in util.get_roi().gen_sites( ['RAMBFIFO36E1']): yield site_name @@ -30,8 +36,12 @@ def gen_brams(): #return #for _tile_name, site_name, _site_type in util.get_roi().gen_tiles(): - for site in gen_bram36(): - yield ('RAMBFIFO36E1', site) + + #for site in gen_bram36(): + # yield ('RAMBFIFO36E1', site) + + for site in gen_bram18(): + yield ('RAMB18E1', site) brams = list(gen_brams()) @@ -58,7 +68,26 @@ def vrandbit(): for loci, (site_type, site) in enumerate(brams): def place_bram18(): - assert 0, 'FIXME' + ports = { + 'clk': 'clk', + 'din': 'din[ %d +: 8]' % (8 * loci, ), + 'dout': 'dout[ %d +: 8]' % (8 * loci, ), + } + params = { + 'LOC': verilog.quote(site), + 'IS_CLKARDCLK_INVERTED': vrandbit(), + 'IS_CLKBWRCLK_INVERTED': vrandbit(), + 'IS_ENARDEN_INVERTED': vrandbit(), + 'IS_ENBWREN_INVERTED': vrandbit(), + 'IS_RSTRAMARSTRAM_INVERTED': vrandbit(), + 'IS_RSTRAMB_INVERTED': vrandbit(), + 'IS_RSTREGARSTREG_INVERTED': vrandbit(), + 'IS_RSTREGB_INVERTED': vrandbit(), + 'RAM_MODE': '"TDP"', + 'WRITE_MODE_A': '"WRITE_FIRST"', + 'WRITE_MODE_B': '"WRITE_FIRST"', + } + return ('my_RAMB18E1', ports, params) def place_bram36(): ports = { @@ -80,24 +109,6 @@ for loci, (site_type, site) in enumerate(brams): 'WRITE_MODE_A': '"WRITE_FIRST"', 'WRITE_MODE_B': '"WRITE_FIRST"', } - if 0: - # FIXME - params = { - 'LOC': verilog.quote(site), - 'IS_CLKARDCLK_INVERTED': "1'b0", - 'IS_CLKBWRCLK_INVERTED': "1'b0", - #'IS_ENARDEN_INVERTED': vrandbit(), - 'IS_ENARDEN_INVERTED': - ("1'b" + str(int(os.getenv("SEEDN")) - 1)), - 'IS_ENBWREN_INVERTED': "1'b0", - 'IS_RSTRAMARSTRAM_INVERTED': "1'b0", - 'IS_RSTRAMB_INVERTED': "1'b0", - 'IS_RSTREGARSTREG_INVERTED': "1'b0", - 'IS_RSTREGB_INVERTED': "1'b0", - 'RAM_MODE': '"TDP"', - 'WRITE_MODE_A': '"WRITE_FIRST"', - 'WRITE_MODE_B': '"WRITE_FIRST"', - } return ('my_RAMB36E1', ports, params) modname, ports, params = { @@ -202,8 +213,7 @@ print( .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), .RAM_MODE(RAM_MODE), .WRITE_MODE_A(WRITE_MODE_A), - .WRITE_MODE_B(WRITE_MODE_B), - .SIM_DEVICE("VIRTEX6") + .WRITE_MODE_B(WRITE_MODE_B) ) ram ( .CLKARDCLK(din[0]), .CLKBWRCLK(din[1]), @@ -270,8 +280,7 @@ print( .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), .RAM_MODE(RAM_MODE), .WRITE_MODE_A(WRITE_MODE_A), - .WRITE_MODE_B(WRITE_MODE_B), - .SIM_DEVICE("VIRTEX6") + .WRITE_MODE_B(WRITE_MODE_B) ) ram ( .CLKARDCLK(din[0]), .CLKBWRCLK(din[1]), diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py index 2aaa82b5..9ef72883 100644 --- a/prjxray/segmaker.py +++ b/prjxray/segmaker.py @@ -228,6 +228,15 @@ class Segmaker: else: assert 0 + def name_bram18(): + # RAMB18_X0Y41 + if re.match(r"RAMB18_X.*Y[0-9]*[02468]", site): + return "RAMB18_Y0" + elif re.match(r"RAMB18_X.*Y[0-9]*[13579]", site): + return "RAMB18_Y1" + else: + assert 0 + def name_default(): # most sites are unique within their tile # TODO: maybe verify against DB? @@ -235,6 +244,7 @@ class Segmaker: sitekey = { 'SLICE': name_slice, + 'RAMB18': name_bram18, }.get(site_prefix, name_default)() for name, value in self.site_tags[site].items():