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Run make format. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-28 16:43:49 -08:00
parent 816bf44156
commit a2d32d19a3
7 changed files with 251 additions and 175 deletions
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3
CONTRIBUTING.md
View File

@ -10,7 +10,8 @@ All contributions should be sent as
### License ### License
All code in the Project X-Ray repository is licensed under the very permissive All software (code, associated documentation, support files, etc) in the
Project X-Ray repository are licensed under the very permissive
[ISC Licence](COPYING). A copy can be found in the [`COPYING`](COPYING) file. [ISC Licence](COPYING). A copy can be found in the [`COPYING`](COPYING) file.
All new contributions must also be released under this license. All new contributions must also be released under this license.

6
fuzzers/030-iob/check_results.py
View File

@ -19,6 +19,7 @@ from prjxray import verilog
import json import json
import generate import generate
def process_parts(parts): def process_parts(parts):
if parts[0] == 'INOUT': if parts[0] == 'INOUT':
yield 'type', 'IOBUF_INTERMDISABLE' yield 'type', 'IOBUF_INTERMDISABLE'
@ -39,6 +40,7 @@ def process_parts(parts):
yield 'IOSTANDARDS', parts[0].split('_') yield 'IOSTANDARDS', parts[0].split('_')
yield 'DRIVES', parts[2].split('_') yield 'DRIVES', parts[2].split('_')
def create_sites_from_fasm(root): def create_sites_from_fasm(root):
sites = {} sites = {}
@ -102,7 +104,8 @@ def process_specimen(root):
assert p['PULLTYPE'] == site_from_fasm['PULLTYPE'], ( assert p['PULLTYPE'] == site_from_fasm['PULLTYPE'], (
tile, site_key, p, site_from_fasm) tile, site_key, p, site_from_fasm)
assert verilog.unquote(p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], ( assert verilog.unquote(
p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], (
tile, site_key, p, site_from_fasm) tile, site_key, p, site_from_fasm)
if p['type'] != 'IBUF': if p['type'] != 'IBUF':
@ -121,5 +124,6 @@ def main():
print('No errors found!') print('No errors found!')
if __name__ == "__main__": if __name__ == "__main__":
main() main()

38
fuzzers/030-iob/generate.py
View File

@ -13,6 +13,7 @@ def bitfilter(frame, word):
return True return True
def mk_drive_opt(iostandard, drive): def mk_drive_opt(iostandard, drive):
return '{}.DRIVE.I{}'.format(iostandard, drive) return '{}.DRIVE.I{}'.format(iostandard, drive)
@ -28,6 +29,7 @@ def skip_broken_tiles(d):
return False return False
def drives_for_iostandard(iostandard): def drives_for_iostandard(iostandard):
if iostandard in ['LVTTL', 'LVCMOS18']: if iostandard in ['LVTTL', 'LVCMOS18']:
drives = [4, 8, 12, 16, 24] drives = [4, 8, 12, 16, 24]
@ -38,6 +40,7 @@ def drives_for_iostandard(iostandard):
return drives return drives
def main(): def main():
print("Loading tags") print("Loading tags")
segmk = Segmaker("design.bits") segmk = Segmaker("design.bits")
@ -63,14 +66,18 @@ def main():
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0) segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0) segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard): for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 0) segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IBUF': elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0) segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1) segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0) segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard): for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 1) segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
elif d['type'] == 'OBUF': elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0) segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
@ -78,9 +85,13 @@ def main():
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1) segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
for drive in drives_for_iostandard(iostandard): for drive in drives_for_iostandard(iostandard):
if drive == d['DRIVE']: if drive == d['DRIVE']:
segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 1) segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
else: else:
segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 0) segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IOBUF_INTERMDISABLE': elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1) segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
@ -88,14 +99,16 @@ def main():
if d['type'] is not None: if d['type'] is not None:
segmaker.add_site_group_zero( segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.", ("NONE", "KEEPER", "PULLDOWN", "PULLUP"), segmk, site, "PULLTYPE.",
"PULLDOWN", verilog.unquote(d['PULLTYPE'])) ("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] == 'IBUF' or d['type'] is None: if d['type'] == 'IBUF' or d['type'] is None:
continue continue
drive_opts = set() drive_opts = set()
for opt in ("LVCMOS25","LVCMOS33", "LVCMOS18", "LVCMOS15", "LVCMOS12", 'LVTTL'): for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"): for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12": if drive_opt == "16" and opt == "LVCMOS12":
continue continue
@ -106,23 +119,24 @@ def main():
drive_opts.add(mk_drive_opt(opt, drive_opt)) drive_opts.add(mk_drive_opt(opt, drive_opt))
segmaker.add_site_group_zero( segmaker.add_site_group_zero(
segmk, site, '', drive_opts, segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE'])) mk_drive_opt(iostandard, d['DRIVE']))
segmaker.add_site_group_zero( segmaker.add_site_group_zero(
segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST", segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST",
verilog.unquote(d['SLEW'])) verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d: if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0') segmk.add_site_tag(
site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d: if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0') segmk.add_site_tag(
site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0')
segmk.compile(bitfilter=bitfilter) segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True) segmk.write(allow_empty=True)
if __name__ == "__main__": if __name__ == "__main__":
main() main()

28
fuzzers/030-iob/process_rdb.py
View File

@ -9,13 +9,16 @@ There are couple cases that need to be handled here:
""" """
import argparse import argparse
def get_name(l): def get_name(l):
parts = l.strip().split(' ') parts = l.strip().split(' ')
return parts[0] return parts[0]
def get_site(l): def get_site(l):
return get_name(l).split('.')[1] return get_name(l).split('.')[1]
def parse_bits(l): def parse_bits(l):
parts = l.strip().split(' ') parts = l.strip().split(' ')
if parts[1] == '<0': if parts[1] == '<0':
@ -23,8 +26,11 @@ def parse_bits(l):
else: else:
return frozenset(parts[1:]) return frozenset(parts[1:])
def main(): def main():
parser = argparse.ArgumentParser(description="Convert IOB rdb into good rdb.""") parser = argparse.ArgumentParser(
description="Convert IOB rdb into good rdb."
"")
parser.add_argument('input_rdb') parser.add_argument('input_rdb')
args = parser.parse_args() args = parser.parse_args()
@ -53,7 +59,6 @@ def main():
drives = {} drives = {}
in_use = {} in_use = {}
for l in iostandard_lines: for l in iostandard_lines:
name = get_name(l) name = get_name(l)
site = get_site(l) site = get_site(l)
@ -76,7 +81,8 @@ def main():
iostandard_in[in_bits].append((site, iostandard)) iostandard_in[in_bits].append((site, iostandard))
if name.endswith('.OUT'): if name.endswith('.OUT'):
outs[(site, iostandard)] = parse_bits(l) | in_use[(site, iostandard)] outs[(site,
iostandard)] = parse_bits(l) | in_use[(site, iostandard)]
if '.DRIVE.' in name and '.IN_OUT_COMMON' not in name: if '.DRIVE.' in name and '.IN_OUT_COMMON' not in name:
drive = name.split('.')[-1] drive = name.split('.')[-1]
@ -96,8 +102,8 @@ def main():
assert len(site) == 1, site assert len(site) == 1, site
site = site.pop() site = site.pop()
print('IOB33.{}.{}.IN'.format(site, '_'.join(standards)), print(
' '.join(bits)) 'IOB33.{}.{}.IN'.format(site, '_'.join(standards)), ' '.join(bits))
iodrives = {} iodrives = {}
@ -105,14 +111,14 @@ def main():
for site, iostandard in drives: for site, iostandard in drives:
for drive in drives[(site, iostandard)]: for drive in drives[(site, iostandard)]:
combined_bits = drives[(site, iostandard)][drive] | outs[(site, iostandard)] combined_bits = drives[(site, iostandard)][drive] | outs[(
site, iostandard)]
if site not in common_bits: if site not in common_bits:
common_bits[site] = set(common_in_bits[site]) common_bits[site] = set(common_in_bits[site])
common_bits[site] |= combined_bits common_bits[site] |= combined_bits
if combined_bits not in iodrives: if combined_bits not in iodrives:
iodrives[combined_bits] = [] iodrives[combined_bits] = []
@ -128,10 +134,10 @@ def main():
neg_bits = set('!' + bit for bit in (common_bits[site] - bits)) neg_bits = set('!' + bit for bit in (common_bits[site] - bits))
print('IOB33.{}.{}.DRIVE.{}'.format( print(
site, 'IOB33.{}.{}.DRIVE.{}'.format(
'_'.join(sorted(set(standards))), site, '_'.join(sorted(set(standards))), '_'.join(
'_'.join(sorted(set(drives)))), ' '.join(bits | neg_bits)) sorted(set(drives)))), ' '.join(bits | neg_bits))
if __name__ == "__main__": if __name__ == "__main__":

44
fuzzers/030-iob/top.py
View File

@ -26,6 +26,7 @@ def gen_sites():
if site_type in ['IOB33S', 'IOB33M']: if site_type in ['IOB33S', 'IOB33M']:
yield tile_name, site_name yield tile_name, site_name
def write_params(params): def write_params(params):
pinstr = 'tile,site,pin,iostandard,drive,slew\n' pinstr = 'tile,site,pin,iostandard,drive,slew\n'
for vals in params: for vals in params:
@ -35,13 +36,17 @@ def write_params(params):
def run(): def run():
tile_types = ['IBUF', 'OBUF', 'IOBUF_INTERMDISABLE', None, None, None, None, None] tile_types = [
'IBUF', 'OBUF', 'IOBUF_INTERMDISABLE', None, None, None, None, None
]
i_idx = 0 i_idx = 0
o_idx = 0 o_idx = 0
io_idx = 0 io_idx = 0
iostandards = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'] iostandards = [
'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
]
iostandard = random.choice(iostandards) iostandard = random.choice(iostandards)
if iostandard in ['LVTTL', 'LVCMOS18']: if iostandard in ['LVTTL', 'LVCMOS18']:
@ -96,16 +101,20 @@ def run():
p['owire'] = luts.get_next_input_net() p['owire'] = luts.get_next_input_net()
p['DRIVE'] = random.choice(drives) p['DRIVE'] = random.choice(drives)
p['SLEW'] = verilog.quote(random.choice(slews)) p['SLEW'] = verilog.quote(random.choice(slews))
p['tristate_wire'] = random.choice(('0', luts.get_next_output_net())) p['tristate_wire'] = random.choice(
p['ibufdisable_wire'] = random.choice(('0', luts.get_next_output_net())) ('0', luts.get_next_output_net()))
p['intermdisable_wire'] = random.choice(('0', luts.get_next_output_net())) p['ibufdisable_wire'] = random.choice(
('0', luts.get_next_output_net()))
p['intermdisable_wire'] = random.choice(
('0', luts.get_next_output_net()))
io_idx += 1 io_idx += 1
params.append(p) params.append(p)
if p['type'] is not None: if p['type'] is not None:
tile_params.append((tile, site, p['pad_wire'], iostandard, tile_params.append(
p['DRIVE'], (
tile, site, p['pad_wire'], iostandard, p['DRIVE'],
verilog.unquote(p['SLEW']) if p['SLEW'] else None, verilog.unquote(p['SLEW']) if p['SLEW'] else None,
verilog.unquote(p['PULLTYPE']))) verilog.unquote(p['PULLTYPE'])))
@ -120,10 +129,7 @@ def run():
module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio); module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio);
(* KEEP, DONT_TOUCH *) (* KEEP, DONT_TOUCH *)
IDELAYCTRL(); IDELAYCTRL();
'''.format( '''.format(n_di=i_idx, n_do=o_idx, n_dio=io_idx))
n_di=i_idx,
n_do=o_idx,
n_dio=io_idx))
# Always output a LUT6 to make placer happy. # Always output a LUT6 to make placer happy.
print(''' print('''
@ -145,13 +151,16 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
) ibuf_{site} ( ) ibuf_{site} (
.I({pad_wire}), .I({pad_wire}),
.O({owire}) .O({owire})
);'''.format(**p), file=connects) );'''.format(**p),
file=connects)
if p['IDELAY_ONLY']: if p['IDELAY_ONLY']:
print(""" print(
"""
(* KEEP, DONT_TOUCH *) (* KEEP, DONT_TOUCH *)
IDELAYE2 idelay_site_{site} ( IDELAYE2 idelay_site_{site} (
.IDATAIN(idelay_{site}) .IDATAIN(idelay_{site})
);""".format(**p), file=connects) );""".format(**p),
file=connects)
elif p['type'] == 'OBUF': elif p['type'] == 'OBUF':
print( print(
@ -164,7 +173,8 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
) ibuf_{site} ( ) ibuf_{site} (
.O({pad_wire}), .O({pad_wire}),
.I({iwire}) .I({iwire})
);'''.format(**p), file=connects) );'''.format(**p),
file=connects)
elif p['type'] == 'IOBUF_INTERMDISABLE': elif p['type'] == 'IOBUF_INTERMDISABLE':
print( print(
''' '''
@ -180,7 +190,8 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
.T({tristate_wire}), .T({tristate_wire}),
.IBUFDISABLE({ibufdisable_wire}), .IBUFDISABLE({ibufdisable_wire}),
.INTERMDISABLE({intermdisable_wire}) .INTERMDISABLE({intermdisable_wire})
);'''.format(**p), file=connects) );'''.format(**p),
file=connects)
for l in luts.create_wires_and_luts(): for l in luts.create_wires_and_luts():
print(l) print(l)
@ -195,4 +206,3 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
if __name__ == '__main__': if __name__ == '__main__':
run() run()

81
fuzzers/035-iob-ilogic/generate.py
View File

@ -4,6 +4,7 @@ from prjxray.segmaker import Segmaker
from prjxray import verilog from prjxray import verilog
import json import json
def handle_data_width(segmk, d): def handle_data_width(segmk, d):
if 'DATA_WIDTH' not in d: if 'DATA_WIDTH' not in d:
return return
@ -12,17 +13,21 @@ def handle_data_width(segmk, d):
return return
for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]: for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]:
segmk.add_site_tag(d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt), segmk.add_site_tag(
d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt),
d['DATA_WIDTH'] == opt) d['DATA_WIDTH'] == opt)
def handle_data_rate(segmk, d): def handle_data_rate(segmk, d):
if 'DATA_WIDTH' not in d: if 'DATA_WIDTH' not in d:
return return
for opt in ['SDR', 'DDR']: for opt in ['SDR', 'DDR']:
segmk.add_site_tag(d['site'], 'ISERDES.DATA_RATE.{}'.format(opt), segmk.add_site_tag(
d['site'], 'ISERDES.DATA_RATE.{}'.format(opt),
verilog.unquote(d['DATA_RATE']) == opt) verilog.unquote(d['DATA_RATE']) == opt)
def main(): def main():
print("Loading tags") print("Loading tags")
segmk = Segmaker("design.bits") segmk = Segmaker("design.bits")
@ -44,7 +49,8 @@ def main():
'NETWORKING', 'NETWORKING',
'OVERSAMPLE', 'OVERSAMPLE',
): ):
segmk.add_site_tag(site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt), segmk.add_site_tag(
site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
opt == verilog.unquote(d['INTERFACE_TYPE'])) opt == verilog.unquote(d['INTERFACE_TYPE']))
if d['iddr_mux_config'] != 'none': if d['iddr_mux_config'] != 'none':
@ -54,51 +60,64 @@ def main():
if 'INIT_Q3' in d: if 'INIT_Q3' in d:
segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3']) segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3'])
segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4']) segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1']) segmk.add_site_tag(
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2']) site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3']) segmk.add_site_tag(
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4']) site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2'])
segmk.add_site_tag(
site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3'])
segmk.add_site_tag(
site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4'])
if 'IS_CLK_INVERTED' in d: if 'IS_CLK_INVERTED' in d:
if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3': if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
segmk.add_site_tag(site, 'IFF.ZINV_CLK', segmk.add_site_tag(
not d['IS_CLK_INVERTED']) site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLKB', segmk.add_site_tag(
not d['IS_CLKB_INVERTED']) site, 'IFF.ZINV_CLKB', not d['IS_CLKB_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLK_XOR', segmk.add_site_tag(
site, 'IFF.ZINV_CLK_XOR',
d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']) d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLK_NXOR', segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NXOR',
not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])) not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
segmk.add_site_tag(site, 'IFF.ZINV_CLK_OR', segmk.add_site_tag(
d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']) site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED']
segmk.add_site_tag(site, 'IFF.ZINV_CLK_NOR', or d['IS_CLKB_INVERTED'])
not (d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED'])) segmk.add_site_tag(
segmk.add_site_tag(site, 'IFF.ZINV_CLK_AND', site, 'IFF.ZINV_CLK_NOR', not (
d['IS_CLK_INVERTED'] and d['IS_CLKB_INVERTED']) d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']))
segmk.add_site_tag(site, 'IFF.ZINV_CLK_NAND', segmk.add_site_tag(
not (d['IS_CLK_INVERTED'] and d['IS_CLKB_INVERTED'])) site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NAND', not (
d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED']))
if 'IS_OCLK_INVERTED' in d: if 'IS_OCLK_INVERTED' in d:
segmk.add_site_tag(site, 'IFF.ZINV_OCLK', segmk.add_site_tag(
not d['IS_OCLK_INVERTED']) site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED'])
if 'IS_C_INVERTED' in d: if 'IS_C_INVERTED' in d:
segmk.add_site_tag(site, 'IFF.ZINV_C', segmk.add_site_tag(
not d['IS_C_INVERTED']) site, 'IFF.ZINV_C', not d['IS_C_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_D', segmk.add_site_tag(site, 'IFF.ZINV_D', not d['IS_D_INVERTED'])
not d['IS_D_INVERTED'])
if 'SRTYPE' in d: if 'SRTYPE' in d:
for opt in ['ASYNC', 'SYNC']: for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site, 'IFF.SRTYPE.{}'.format(opt), segmk.add_site_tag(
site, 'IFF.SRTYPE.{}'.format(opt),
verilog.unquote(d['SRTYPE']) == opt) verilog.unquote(d['SRTYPE']) == opt)
if 'DDR_CLK_EDGE' in d: if 'DDR_CLK_EDGE' in d:
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE', 'SAME_EDGE_PIPELINED']: for opt in ['OPPOSITE_EDGE', 'SAME_EDGE',
segmk.add_site_tag(site, 'IFF.DDR_CLK_EDGE.{}'.format(opt), 'SAME_EDGE_PIPELINED']:
segmk.add_site_tag(
site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['DDR_CLK_EDGE']) == opt) verilog.unquote(d['DDR_CLK_EDGE']) == opt)
ofb_used = False ofb_used = False
@ -163,9 +182,9 @@ def main():
else: else:
assert False, d['mux_config'] assert False, d['mux_config']
segmk.compile() segmk.compile()
segmk.write(allow_empty=True) segmk.write(allow_empty=True)
if __name__ == "__main__": if __name__ == "__main__":
main() main()

114
fuzzers/035-iob-ilogic/top.py
View File

@ -26,6 +26,7 @@ def gen_sites():
if site_type in ['IOB33S', 'IOB33M']: if site_type in ['IOB33S', 'IOB33M']:
yield tile_name, site_name yield tile_name, site_name
def write_params(params): def write_params(params):
pinstr = 'tile,site,pin,iostandard,drive,slew\n' pinstr = 'tile,site,pin,iostandard,drive,slew\n'
for vals in params: for vals in params:
@ -33,6 +34,7 @@ def write_params(params):
open('params.csv', 'w').write(pinstr) open('params.csv', 'w').write(pinstr)
def use_iserdese2(p, luts, connects): def use_iserdese2(p, luts, connects):
iobdelay = random.choice(( iobdelay = random.choice((
'NONE', 'NONE',
@ -57,7 +59,9 @@ def use_iserdese2(p, luts, connects):
p['IS_CLKB_INVERTED'] = random.randint(0, 1) p['IS_CLKB_INVERTED'] = random.randint(0, 1)
p['IS_OCLK_INVERTED'] = random.randint(0, 1) p['IS_OCLK_INVERTED'] = random.randint(0, 1)
p['IS_D_INVERTED'] = random.randint(0, 1) p['IS_D_INVERTED'] = random.randint(0, 1)
p['INTERFACE_TYPE'] = verilog.quote(random.choice(( p['INTERFACE_TYPE'] = verilog.quote(
random.choice(
(
'MEMORY', 'MEMORY',
'MEMORY_DDR3', 'MEMORY_DDR3',
'MEMORY_QDR', 'MEMORY_QDR',
@ -96,7 +100,8 @@ def use_iserdese2(p, luts, connects):
p['DYN_CLK_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE'))) p['DYN_CLK_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE')))
if use_delay: if use_delay:
print(""" print(
"""
wire idelay_{site}; wire idelay_{site};
(* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *) (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *)
@ -104,8 +109,8 @@ def use_iserdese2(p, luts, connects):
) idelay_site_{site} ( ) idelay_site_{site} (
.IDATAIN({iwire}), .IDATAIN({iwire}),
.DATAOUT(idelay_{site}) .DATAOUT(idelay_{site})
);""".format( );""".format(**p),
**p), file=connects) file=connects)
p['ddly_connection'] = '.DDLY(idelay_{site}),'.format(**p) p['ddly_connection'] = '.DDLY(idelay_{site}),'.format(**p)
else: else:
@ -129,8 +134,8 @@ def use_iserdese2(p, luts, connects):
else: else:
p['TRISTATE_WIDTH'] = 4 p['TRISTATE_WIDTH'] = 4
print(
print(""" """
wire tfb_{site}; wire tfb_{site};
wire ofb_{site}; wire ofb_{site};
@ -149,8 +154,8 @@ def use_iserdese2(p, luts, connects):
.OQ({owire}), .OQ({owire}),
.TQ({twire}), .TQ({twire}),
.OFB(ofb_{site}) .OFB(ofb_{site})
);""".format( );""".format(**p),
**p), file=connects) file=connects)
p['ofb_connections'] = """ p['ofb_connections'] = """
.OFB(ofb_{site}), .OFB(ofb_{site}),
@ -158,8 +163,8 @@ def use_iserdese2(p, luts, connects):
else: else:
p['ofb_connections'] = '' p['ofb_connections'] = ''
print(
print(''' '''
(* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *)
ISERDESE2 #( ISERDESE2 #(
.SERDES_MODE({SERDES_MODE}), .SERDES_MODE({SERDES_MODE}),
@ -200,7 +205,8 @@ def use_iserdese2(p, luts, connects):
q1net=luts.get_next_input_net(), q1net=luts.get_next_input_net(),
shiftout1net=luts.get_next_input_net(), shiftout1net=luts.get_next_input_net(),
shiftout2net=luts.get_next_input_net(), shiftout2net=luts.get_next_input_net(),
**p), file=connects) **p),
file=connects)
def use_direct_and_iddr(p, luts, connects): def use_direct_and_iddr(p, luts, connects):
@ -222,13 +228,16 @@ def use_direct_and_iddr(p, luts, connects):
p['IS_C_INVERTED'] = random.randint(0, 1) p['IS_C_INVERTED'] = random.randint(0, 1)
p['IS_D_INVERTED'] = random.randint(0, 1) p['IS_D_INVERTED'] = random.randint(0, 1)
p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC'))) p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
p['DDR_CLK_EDGE'] = verilog.quote(random.choice(( p['DDR_CLK_EDGE'] = verilog.quote(
random.choice(
(
'OPPOSITE_EDGE', 'OPPOSITE_EDGE',
'SAME_EDGE', 'SAME_EDGE',
'SAME_EDGE_PIPELINED', 'SAME_EDGE_PIPELINED',
))) )))
print(''' print(
'''
(* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *)
IDDR #( IDDR #(
.IS_D_INVERTED({IS_D_INVERTED}), .IS_D_INVERTED({IS_D_INVERTED}),
@ -247,10 +256,13 @@ def use_direct_and_iddr(p, luts, connects):
cnet=luts.get_next_output_net(), cnet=luts.get_next_output_net(),
q1=luts.get_next_input_net(), q1=luts.get_next_input_net(),
q2=luts.get_next_input_net(), q2=luts.get_next_input_net(),
**p), file=connects) **p),
file=connects)
if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p['iddr_mux_config'] == 'tristate_feedback': if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p[
print(""" 'iddr_mux_config'] == 'tristate_feedback':
print(
"""
wire idelay_{site}; wire idelay_{site};
(* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *) (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *)
@ -258,56 +270,66 @@ def use_direct_and_iddr(p, luts, connects):
) idelay_site_{site} ( ) idelay_site_{site} (
.IDATAIN({iwire}), .IDATAIN({iwire}),
.DATAOUT(idelay_{site}) .DATAOUT(idelay_{site})
);""".format( );""".format(**p),
**p), file=connects) file=connects)
print(""" print(
"""
assign {owire} = {onet}; assign {owire} = {onet};
assign {twire} = {tnet}; assign {twire} = {tnet};
""".format( """.format(
onet=luts.get_next_output_net(), onet=luts.get_next_output_net(),
tnet=luts.get_next_output_net(), tnet=luts.get_next_output_net(),
**p), file=connects) **p),
file=connects)
if p['iddr_mux_config'] == 'direct': if p['iddr_mux_config'] == 'direct':
print(''' print(
assign iddr_d_{site} = {iwire};'''.format( '''
**p, assign iddr_d_{site} = {iwire};'''.format(**p, ),
), file=connects) file=connects)
elif p['iddr_mux_config'] == 'idelay': elif p['iddr_mux_config'] == 'idelay':
print(''' print(
assign iddr_d_{site} = idelay_{site};'''.format( '''
**p, assign iddr_d_{site} = idelay_{site};'''.format(**p, ),
), file=connects) file=connects)
elif p['iddr_mux_config'] == 'tristate_feedback': elif p['iddr_mux_config'] == 'tristate_feedback':
print(''' print(
'''
assign iddr_d_{site} = tfb_{site} ? ofb_{site} : idelay_{site};'''.format( assign iddr_d_{site} = tfb_{site} ? ofb_{site} : idelay_{site};'''.format(
**p, **p, ),
), file=connects) file=connects)
elif p['iddr_mux_config'] == 'none': elif p['iddr_mux_config'] == 'none':
pass pass
else: else:
assert False, p['mux_config'] assert False, p['mux_config']
if p['mux_config'] == 'direct': if p['mux_config'] == 'direct':
print(''' print(
'''
assign {net} = {iwire};'''.format( assign {net} = {iwire};'''.format(
net=luts.get_next_input_net(), net=luts.get_next_input_net(),
**p, **p,
), file=connects) ),
file=connects)
elif p['mux_config'] == 'idelay': elif p['mux_config'] == 'idelay':
print(''' print(
'''
assign {net} = idelay_{site};'''.format( assign {net} = idelay_{site};'''.format(
net=luts.get_next_input_net(), net=luts.get_next_input_net(),
**p, **p,
), file=connects) ),
file=connects)
elif p['mux_config'] == 'none': elif p['mux_config'] == 'none':
pass pass
else: else:
assert False, p['mux_config'] assert False, p['mux_config']
def run(): def run():
iostandards = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'] iostandards = [
'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
]
iostandard = random.choice(iostandards) iostandard = random.choice(iostandards)
if iostandard in ['LVTTL', 'LVCMOS18']: if iostandard in ['LVTTL', 'LVCMOS18']:
@ -330,7 +352,6 @@ def run():
if idx == 0: if idx == 0:
continue continue
p = {} p = {}
p['tile'] = tile p['tile'] = tile
p['site'] = site p['site'] = site
@ -348,8 +369,9 @@ def run():
p['twire'] = 't[{}]'.format(idx - 1) p['twire'] = 't[{}]'.format(idx - 1)
params.append(p) params.append(p)
tile_params.append((tile, site, p['pad_wire'], iostandard, tile_params.append(
p['DRIVE'], (
tile, site, p['pad_wire'], iostandard, p['DRIVE'],
verilog.unquote(p['SLEW']) if p['SLEW'] else None, verilog.unquote(p['SLEW']) if p['SLEW'] else None,
verilog.unquote(p['PULLTYPE']))) verilog.unquote(p['PULLTYPE'])))
@ -363,11 +385,11 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
wire [`N_DI-1:0] di_buf; wire [`N_DI-1:0] di_buf;
wire [`N_DI-1:0] do_buf; wire [`N_DI-1:0] do_buf;
wire [`N_DI-1:0] t; wire [`N_DI-1:0] t;
'''.format( '''.format(n_di=idx))
n_di=idx))
# Always output a LUT6 to make placer happy. # Always output a LUT6 to make placer happy.
print(''' print(
'''
(* KEEP, DONT_TOUCH *) (* KEEP, DONT_TOUCH *)
LUT6 dummy_lut(); LUT6 dummy_lut();
''') ''')
@ -375,7 +397,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
any_idelay = False any_idelay = False
for p in params: for p in params:
print(''' print(
'''
wire iddr_d_{site}; wire iddr_d_{site};
(* KEEP, DONT_TOUCH, LOC = "{site}" *) (* KEEP, DONT_TOUCH, LOC = "{site}" *)
@ -387,8 +410,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
.O({iwire}), .O({iwire}),
.T({twire}) .T({twire})
); );
'''.format( '''.format(**p),
**p), file=connects) file=connects)
p['use_iserdese2'] = random.randint(0, 1) p['use_iserdese2'] = random.randint(0, 1)
if p['use_iserdese2']: if p['use_iserdese2']:
@ -417,4 +440,3 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
if __name__ == '__main__': if __name__ == '__main__':
run() run()