From a2d32d19a3e39eac0cdbcf975bf19e236dd20bf7 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 28 Feb 2019 16:43:49 -0800 Subject: [PATCH] Run make format. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- CONTRIBUTING.md | 3 +- fuzzers/030-iob/check_results.py | 20 ++-- fuzzers/030-iob/generate.py | 38 ++++-- fuzzers/030-iob/process_rdb.py | 34 +++--- fuzzers/030-iob/top.py | 48 +++++--- fuzzers/035-iob-ilogic/generate.py | 99 +++++++++------- fuzzers/035-iob-ilogic/top.py | 184 ++++++++++++++++------------- 7 files changed, 251 insertions(+), 175 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 4b7acc0a..9acd526e 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -10,7 +10,8 @@ All contributions should be sent as ### License -All code in the Project X-Ray repository is licensed under the very permissive +All software (code, associated documentation, support files, etc) in the +Project X-Ray repository are licensed under the very permissive [ISC Licence](COPYING). A copy can be found in the [`COPYING`](COPYING) file. All new contributions must also be released under this license. diff --git a/fuzzers/030-iob/check_results.py b/fuzzers/030-iob/check_results.py index 2369e628..affe8942 100644 --- a/fuzzers/030-iob/check_results.py +++ b/fuzzers/030-iob/check_results.py @@ -19,6 +19,7 @@ from prjxray import verilog import json import generate + def process_parts(parts): if parts[0] == 'INOUT': yield 'type', 'IOBUF_INTERMDISABLE' @@ -39,6 +40,7 @@ def process_parts(parts): yield 'IOSTANDARDS', parts[0].split('_') yield 'DRIVES', parts[2].split('_') + def create_sites_from_fasm(root): sites = {} @@ -52,9 +54,9 @@ def create_sites_from_fasm(root): site = parts[1] if (tile, site) not in sites: sites[(tile, site)] = { - 'tile': tile, - 'site_key': site, - } + 'tile': tile, + 'site_key': site, + } for key, value in process_parts(parts[2:]): sites[(tile, site)][key] = value @@ -80,7 +82,7 @@ def process_specimen(root): for p in params: tile = p['tile'] site = p['site'] - site_y = int(site[site.find('Y')+1:]) % 2 + site_y = int(site[site.find('Y') + 1:]) % 2 if generate.skip_broken_tiles(p): continue @@ -94,20 +96,21 @@ def process_specimen(root): site_from_fasm = sites[(tile, site_key)] assert p['type'] == site_from_fasm['type'], ( - tile, site_key, p, site_from_fasm) + tile, site_key, p, site_from_fasm) if p['type'] is None: continue assert p['PULLTYPE'] == site_from_fasm['PULLTYPE'], ( - tile, site_key, p, site_from_fasm) + tile, site_key, p, site_from_fasm) - assert verilog.unquote(p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], ( + assert verilog.unquote( + p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], ( tile, site_key, p, site_from_fasm) if p['type'] != 'IBUF': assert p['SLEW'] == site_from_fasm['SLEW'], ( - tile, site_key, p, site_from_fasm) + tile, site_key, p, site_from_fasm) assert 'I{}'.format(p['DRIVE']) in site_from_fasm['DRIVES'], ( tile, site_key, p, site_from_fasm) @@ -121,5 +124,6 @@ def main(): print('No errors found!') + if __name__ == "__main__": main() diff --git a/fuzzers/030-iob/generate.py b/fuzzers/030-iob/generate.py index 0fe9e9ca..7ad44b2c 100644 --- a/fuzzers/030-iob/generate.py +++ b/fuzzers/030-iob/generate.py @@ -13,6 +13,7 @@ def bitfilter(frame, word): return True + def mk_drive_opt(iostandard, drive): return '{}.DRIVE.I{}'.format(iostandard, drive) @@ -28,6 +29,7 @@ def skip_broken_tiles(d): return False + def drives_for_iostandard(iostandard): if iostandard in ['LVTTL', 'LVCMOS18']: drives = [4, 8, 12, 16, 24] @@ -38,6 +40,7 @@ def drives_for_iostandard(iostandard): return drives + def main(): print("Loading tags") segmk = Segmaker("design.bits") @@ -63,14 +66,18 @@ def main(): segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0) segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0) for drive in drives_for_iostandard(iostandard): - segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 0) + segmk.add_site_tag( + site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format( + iostandard, drive), 0) elif d['type'] == 'IBUF': segmk.add_site_tag(site, 'INOUT', 0) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1) segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1) segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0) for drive in drives_for_iostandard(iostandard): - segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 1) + segmk.add_site_tag( + site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format( + iostandard, drive), 1) elif d['type'] == 'OBUF': segmk.add_site_tag(site, 'INOUT', 0) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1) @@ -78,9 +85,13 @@ def main(): segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1) for drive in drives_for_iostandard(iostandard): if drive == d['DRIVE']: - segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 1) + segmk.add_site_tag( + site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format( + iostandard, drive), 1) else: - segmk.add_site_tag(site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard, drive), 0) + segmk.add_site_tag( + site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format( + iostandard, drive), 0) elif d['type'] == 'IOBUF_INTERMDISABLE': segmk.add_site_tag(site, 'INOUT', 1) segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1) @@ -88,14 +99,16 @@ def main(): if d['type'] is not None: segmaker.add_site_group_zero( - segmk, site, "PULLTYPE.", ("NONE", "KEEPER", "PULLDOWN", "PULLUP"), - "PULLDOWN", verilog.unquote(d['PULLTYPE'])) + segmk, site, "PULLTYPE.", + ("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN", + verilog.unquote(d['PULLTYPE'])) if d['type'] == 'IBUF' or d['type'] is None: continue drive_opts = set() - for opt in ("LVCMOS25","LVCMOS33", "LVCMOS18", "LVCMOS15", "LVCMOS12", 'LVTTL'): + for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15", + "LVCMOS12", 'LVTTL'): for drive_opt in ("4", "8", "12", "16", "24"): if drive_opt == "16" and opt == "LVCMOS12": continue @@ -106,23 +119,24 @@ def main(): drive_opts.add(mk_drive_opt(opt, drive_opt)) segmaker.add_site_group_zero( - segmk, site, '', drive_opts, - mk_drive_opt('LVCMOS25', '12'), + segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'), mk_drive_opt(iostandard, d['DRIVE'])) - segmaker.add_site_group_zero( segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST", verilog.unquote(d['SLEW'])) if 'ibufdisable_wire' in d: - segmk.add_site_tag(site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0') + segmk.add_site_tag( + site, 'IBUFDISABLE.I', d['ibufdisable_wire'] != '0') if 'intermdisable_wire' in d: - segmk.add_site_tag(site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0') + segmk.add_site_tag( + site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0') segmk.compile(bitfilter=bitfilter) segmk.write(allow_empty=True) + if __name__ == "__main__": main() diff --git a/fuzzers/030-iob/process_rdb.py b/fuzzers/030-iob/process_rdb.py index 1ae5c2cc..3712e34b 100644 --- a/fuzzers/030-iob/process_rdb.py +++ b/fuzzers/030-iob/process_rdb.py @@ -9,13 +9,16 @@ There are couple cases that need to be handled here: """ import argparse + def get_name(l): parts = l.strip().split(' ') return parts[0] + def get_site(l): return get_name(l).split('.')[1] + def parse_bits(l): parts = l.strip().split(' ') if parts[1] == '<0': @@ -23,8 +26,11 @@ def parse_bits(l): else: return frozenset(parts[1:]) + def main(): - parser = argparse.ArgumentParser(description="Convert IOB rdb into good rdb.""") + parser = argparse.ArgumentParser( + description="Convert IOB rdb into good rdb." + "") parser.add_argument('input_rdb') args = parser.parse_args() @@ -38,9 +44,9 @@ def main(): print(l.strip()) common_in_bits = { - 'IOB_Y0': set(), - 'IOB_Y1': set(), - } + 'IOB_Y0': set(), + 'IOB_Y1': set(), + } for l in iostandard_lines: if 'IN_OUT_COMMON' in l: common_in_bits[get_site(l)] |= parse_bits(l) @@ -53,7 +59,6 @@ def main(): drives = {} in_use = {} - for l in iostandard_lines: name = get_name(l) site = get_site(l) @@ -76,7 +81,8 @@ def main(): iostandard_in[in_bits].append((site, iostandard)) if name.endswith('.OUT'): - outs[(site, iostandard)] = parse_bits(l) | in_use[(site, iostandard)] + outs[(site, + iostandard)] = parse_bits(l) | in_use[(site, iostandard)] if '.DRIVE.' in name and '.IN_OUT_COMMON' not in name: drive = name.split('.')[-1] @@ -96,8 +102,8 @@ def main(): assert len(site) == 1, site site = site.pop() - print('IOB33.{}.{}.IN'.format(site, '_'.join(standards)), - ' '.join(bits)) + print( + 'IOB33.{}.{}.IN'.format(site, '_'.join(standards)), ' '.join(bits)) iodrives = {} @@ -105,14 +111,14 @@ def main(): for site, iostandard in drives: for drive in drives[(site, iostandard)]: - combined_bits = drives[(site, iostandard)][drive] | outs[(site, iostandard)] + combined_bits = drives[(site, iostandard)][drive] | outs[( + site, iostandard)] if site not in common_bits: common_bits[site] = set(common_in_bits[site]) common_bits[site] |= combined_bits - if combined_bits not in iodrives: iodrives[combined_bits] = [] @@ -128,10 +134,10 @@ def main(): neg_bits = set('!' + bit for bit in (common_bits[site] - bits)) - print('IOB33.{}.{}.DRIVE.{}'.format( - site, - '_'.join(sorted(set(standards))), - '_'.join(sorted(set(drives)))), ' '.join(bits | neg_bits)) + print( + 'IOB33.{}.{}.DRIVE.{}'.format( + site, '_'.join(sorted(set(standards))), '_'.join( + sorted(set(drives)))), ' '.join(bits | neg_bits)) if __name__ == "__main__": diff --git a/fuzzers/030-iob/top.py b/fuzzers/030-iob/top.py index 9f3cc311..e89456d6 100644 --- a/fuzzers/030-iob/top.py +++ b/fuzzers/030-iob/top.py @@ -26,6 +26,7 @@ def gen_sites(): if site_type in ['IOB33S', 'IOB33M']: yield tile_name, site_name + def write_params(params): pinstr = 'tile,site,pin,iostandard,drive,slew\n' for vals in params: @@ -35,13 +36,17 @@ def write_params(params): def run(): - tile_types = ['IBUF', 'OBUF', 'IOBUF_INTERMDISABLE', None, None, None, None, None] + tile_types = [ + 'IBUF', 'OBUF', 'IOBUF_INTERMDISABLE', None, None, None, None, None + ] i_idx = 0 o_idx = 0 io_idx = 0 - iostandards = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'] + iostandards = [ + 'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL' + ] iostandard = random.choice(iostandards) if iostandard in ['LVTTL', 'LVCMOS18']: @@ -96,18 +101,22 @@ def run(): p['owire'] = luts.get_next_input_net() p['DRIVE'] = random.choice(drives) p['SLEW'] = verilog.quote(random.choice(slews)) - p['tristate_wire'] = random.choice(('0', luts.get_next_output_net())) - p['ibufdisable_wire'] = random.choice(('0', luts.get_next_output_net())) - p['intermdisable_wire'] = random.choice(('0', luts.get_next_output_net())) + p['tristate_wire'] = random.choice( + ('0', luts.get_next_output_net())) + p['ibufdisable_wire'] = random.choice( + ('0', luts.get_next_output_net())) + p['intermdisable_wire'] = random.choice( + ('0', luts.get_next_output_net())) io_idx += 1 params.append(p) if p['type'] is not None: - tile_params.append((tile, site, p['pad_wire'], iostandard, - p['DRIVE'], - verilog.unquote(p['SLEW']) if p['SLEW'] else None, - verilog.unquote(p['PULLTYPE']))) + tile_params.append( + ( + tile, site, p['pad_wire'], iostandard, p['DRIVE'], + verilog.unquote(p['SLEW']) if p['SLEW'] else None, + verilog.unquote(p['PULLTYPE']))) write_params(tile_params) @@ -120,10 +129,7 @@ def run(): module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio); (* KEEP, DONT_TOUCH *) IDELAYCTRL(); - '''.format( - n_di=i_idx, - n_do=o_idx, - n_dio=io_idx)) + '''.format(n_di=i_idx, n_do=o_idx, n_dio=io_idx)) # Always output a LUT6 to make placer happy. print(''' @@ -145,13 +151,16 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N ) ibuf_{site} ( .I({pad_wire}), .O({owire}) - );'''.format(**p), file=connects) + );'''.format(**p), + file=connects) if p['IDELAY_ONLY']: - print(""" + print( + """ (* KEEP, DONT_TOUCH *) IDELAYE2 idelay_site_{site} ( .IDATAIN(idelay_{site}) - );""".format(**p), file=connects) + );""".format(**p), + file=connects) elif p['type'] == 'OBUF': print( @@ -164,7 +173,8 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N ) ibuf_{site} ( .O({pad_wire}), .I({iwire}) - );'''.format(**p), file=connects) + );'''.format(**p), + file=connects) elif p['type'] == 'IOBUF_INTERMDISABLE': print( ''' @@ -180,7 +190,8 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N .T({tristate_wire}), .IBUFDISABLE({ibufdisable_wire}), .INTERMDISABLE({intermdisable_wire}) - );'''.format(**p), file=connects) + );'''.format(**p), + file=connects) for l in luts.create_wires_and_luts(): print(l) @@ -195,4 +206,3 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N if __name__ == '__main__': run() - diff --git a/fuzzers/035-iob-ilogic/generate.py b/fuzzers/035-iob-ilogic/generate.py index cb9424a2..54610837 100644 --- a/fuzzers/035-iob-ilogic/generate.py +++ b/fuzzers/035-iob-ilogic/generate.py @@ -4,6 +4,7 @@ from prjxray.segmaker import Segmaker from prjxray import verilog import json + def handle_data_width(segmk, d): if 'DATA_WIDTH' not in d: return @@ -11,17 +12,21 @@ def handle_data_width(segmk, d): if d['DATA_RATE'] == 'DDR': return - for opt in [2, 3, 4,5, 6, 7, 8, 10, 14]: - segmk.add_site_tag(d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt), - d['DATA_WIDTH'] == opt) + for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]: + segmk.add_site_tag( + d['site'], 'ISERDES.DATA_WIDTH.{}'.format(opt), + d['DATA_WIDTH'] == opt) + def handle_data_rate(segmk, d): if 'DATA_WIDTH' not in d: return for opt in ['SDR', 'DDR']: - segmk.add_site_tag(d['site'], 'ISERDES.DATA_RATE.{}'.format(opt), - verilog.unquote(d['DATA_RATE']) == opt) + segmk.add_site_tag( + d['site'], 'ISERDES.DATA_RATE.{}'.format(opt), + verilog.unquote(d['DATA_RATE']) == opt) + def main(): print("Loading tags") @@ -43,9 +48,10 @@ def main(): 'MEMORY_QDR', 'NETWORKING', 'OVERSAMPLE', - ): - segmk.add_site_tag(site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt), - opt == verilog.unquote(d['INTERFACE_TYPE'])) + ): + segmk.add_site_tag( + site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt), + opt == verilog.unquote(d['INTERFACE_TYPE'])) if d['iddr_mux_config'] != 'none': segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1']) @@ -54,52 +60,65 @@ def main(): if 'INIT_Q3' in d: segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3']) segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4']) - segmk.add_site_tag(site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1']) - segmk.add_site_tag(site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2']) - segmk.add_site_tag(site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3']) - segmk.add_site_tag(site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4']) if 'IS_CLK_INVERTED' in d: if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3': - segmk.add_site_tag(site, 'IFF.ZINV_CLK', - not d['IS_CLK_INVERTED']) - segmk.add_site_tag(site, 'IFF.ZINV_CLKB', - not d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLKB', not d['IS_CLKB_INVERTED']) - segmk.add_site_tag(site, 'IFF.ZINV_CLK_XOR', - d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']) - segmk.add_site_tag(site, 'IFF.ZINV_CLK_NXOR', - not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_XOR', + d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_NXOR', + not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])) - segmk.add_site_tag(site, 'IFF.ZINV_CLK_OR', - d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED']) - segmk.add_site_tag(site, 'IFF.ZINV_CLK_NOR', - not (d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED'])) - segmk.add_site_tag(site, 'IFF.ZINV_CLK_AND', - d['IS_CLK_INVERTED'] and d['IS_CLKB_INVERTED']) - segmk.add_site_tag(site, 'IFF.ZINV_CLK_NAND', - not (d['IS_CLK_INVERTED'] and d['IS_CLKB_INVERTED'])) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED'] + or d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_NOR', not ( + d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED'])) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED'] + and d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_NAND', not ( + d['IS_CLK_INVERTED'] + and d['IS_CLKB_INVERTED'])) if 'IS_OCLK_INVERTED' in d: - segmk.add_site_tag(site, 'IFF.ZINV_OCLK', - not d['IS_OCLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED']) if 'IS_C_INVERTED' in d: - segmk.add_site_tag(site, 'IFF.ZINV_C', - not d['IS_C_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_C', not d['IS_C_INVERTED']) - segmk.add_site_tag(site, 'IFF.ZINV_D', - not d['IS_D_INVERTED']) + segmk.add_site_tag(site, 'IFF.ZINV_D', not d['IS_D_INVERTED']) if 'SRTYPE' in d: for opt in ['ASYNC', 'SYNC']: - segmk.add_site_tag(site, 'IFF.SRTYPE.{}'.format(opt), - verilog.unquote(d['SRTYPE']) == opt) + segmk.add_site_tag( + site, 'IFF.SRTYPE.{}'.format(opt), + verilog.unquote(d['SRTYPE']) == opt) if 'DDR_CLK_EDGE' in d: - for opt in ['OPPOSITE_EDGE', 'SAME_EDGE', 'SAME_EDGE_PIPELINED']: - segmk.add_site_tag(site, 'IFF.DDR_CLK_EDGE.{}'.format(opt), - verilog.unquote(d['DDR_CLK_EDGE']) == opt) + for opt in ['OPPOSITE_EDGE', 'SAME_EDGE', + 'SAME_EDGE_PIPELINED']: + segmk.add_site_tag( + site, 'IFF.DDR_CLK_EDGE.{}'.format(opt), + verilog.unquote(d['DDR_CLK_EDGE']) == opt) ofb_used = False if 'OFB_USED' in d and d['OFB_USED']: @@ -163,9 +182,9 @@ def main(): else: assert False, d['mux_config'] - segmk.compile() segmk.write(allow_empty=True) + if __name__ == "__main__": main() diff --git a/fuzzers/035-iob-ilogic/top.py b/fuzzers/035-iob-ilogic/top.py index 97c224fe..4404bdd9 100644 --- a/fuzzers/035-iob-ilogic/top.py +++ b/fuzzers/035-iob-ilogic/top.py @@ -26,6 +26,7 @@ def gen_sites(): if site_type in ['IOB33S', 'IOB33M']: yield tile_name, site_name + def write_params(params): pinstr = 'tile,site,pin,iostandard,drive,slew\n' for vals in params: @@ -33,13 +34,14 @@ def write_params(params): open('params.csv', 'w').write(pinstr) + def use_iserdese2(p, luts, connects): iobdelay = random.choice(( 'NONE', 'BOTH', 'IBUF', 'IFD', - )) + )) p['IOBDELAY'] = verilog.quote(iobdelay) p['INIT_Q1'] = random.randint(0, 1) @@ -57,17 +59,19 @@ def use_iserdese2(p, luts, connects): p['IS_CLKB_INVERTED'] = random.randint(0, 1) p['IS_OCLK_INVERTED'] = random.randint(0, 1) p['IS_D_INVERTED'] = random.randint(0, 1) - p['INTERFACE_TYPE'] = verilog.quote(random.choice(( - 'MEMORY', - 'MEMORY_DDR3', - 'MEMORY_QDR', - 'NETWORKING', - 'OVERSAMPLE', - ))) + p['INTERFACE_TYPE'] = verilog.quote( + random.choice( + ( + 'MEMORY', + 'MEMORY_DDR3', + 'MEMORY_QDR', + 'NETWORKING', + 'OVERSAMPLE', + ))) p['DATA_RATE'] = verilog.quote(random.choice(( 'SDR', 'DDR', - ))) + ))) if verilog.unquote(p['DATA_RATE']) == 'SDR': data_widths = [2, 3, 4, 5, 6, 7, 8] else: @@ -96,7 +100,8 @@ def use_iserdese2(p, luts, connects): p['DYN_CLK_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE'))) if use_delay: - print(""" + print( + """ wire idelay_{site}; (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *) @@ -104,8 +109,8 @@ def use_iserdese2(p, luts, connects): ) idelay_site_{site} ( .IDATAIN({iwire}), .DATAOUT(idelay_{site}) - );""".format( - **p), file=connects) + );""".format(**p), + file=connects) p['ddly_connection'] = '.DDLY(idelay_{site}),'.format(**p) else: @@ -115,7 +120,7 @@ def use_iserdese2(p, luts, connects): p['ODATA_RATE'] = verilog.quote(random.choice(( 'SDR', 'DDR', - ))) + ))) if verilog.unquote(p['ODATA_RATE']) == 'SDR': data_widths = [2, 3, 4, 5, 6, 7, 8] else: @@ -129,8 +134,8 @@ def use_iserdese2(p, luts, connects): else: p['TRISTATE_WIDTH'] = 4 - - print(""" + print( + """ wire tfb_{site}; wire ofb_{site}; @@ -149,8 +154,8 @@ def use_iserdese2(p, luts, connects): .OQ({owire}), .TQ({twire}), .OFB(ofb_{site}) - );""".format( - **p), file=connects) + );""".format(**p), + file=connects) p['ofb_connections'] = """ .OFB(ofb_{site}), @@ -158,8 +163,8 @@ def use_iserdese2(p, luts, connects): else: p['ofb_connections'] = '' - - print(''' + print( + ''' (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) ISERDESE2 #( .SERDES_MODE({SERDES_MODE}), @@ -193,14 +198,15 @@ def use_iserdese2(p, luts, connects): .Q1({q1net}), .CLKDIV(0) );'''.format( - clknet=luts.get_next_output_net(), - clkbnet=luts.get_next_output_net(), - oclknet=luts.get_next_output_net(), - onet=luts.get_next_input_net(), - q1net=luts.get_next_input_net(), - shiftout1net=luts.get_next_input_net(), - shiftout2net=luts.get_next_input_net(), - **p), file=connects) + clknet=luts.get_next_output_net(), + clkbnet=luts.get_next_output_net(), + oclknet=luts.get_next_output_net(), + onet=luts.get_next_input_net(), + q1net=luts.get_next_input_net(), + shiftout1net=luts.get_next_input_net(), + shiftout2net=luts.get_next_input_net(), + **p), + file=connects) def use_direct_and_iddr(p, luts, connects): @@ -208,13 +214,13 @@ def use_direct_and_iddr(p, luts, connects): 'direct', 'idelay', 'none', - )) + )) p['iddr_mux_config'] = random.choice(( 'direct', 'idelay', 'none', - )) + )) if p['iddr_mux_config'] != 'none': p['INIT_Q1'] = random.randint(0, 1) @@ -222,13 +228,16 @@ def use_direct_and_iddr(p, luts, connects): p['IS_C_INVERTED'] = random.randint(0, 1) p['IS_D_INVERTED'] = random.randint(0, 1) p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC'))) - p['DDR_CLK_EDGE'] = verilog.quote(random.choice(( - 'OPPOSITE_EDGE', - 'SAME_EDGE', - 'SAME_EDGE_PIPELINED', - ))) + p['DDR_CLK_EDGE'] = verilog.quote( + random.choice( + ( + 'OPPOSITE_EDGE', + 'SAME_EDGE', + 'SAME_EDGE_PIPELINED', + ))) - print(''' + print( + ''' (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) IDDR #( .IS_D_INVERTED({IS_D_INVERTED}), @@ -244,13 +253,16 @@ def use_direct_and_iddr(p, luts, connects): .Q2({q2}) ); '''.format( - cnet=luts.get_next_output_net(), - q1=luts.get_next_input_net(), - q2=luts.get_next_input_net(), - **p), file=connects) + cnet=luts.get_next_output_net(), + q1=luts.get_next_input_net(), + q2=luts.get_next_input_net(), + **p), + file=connects) - if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p['iddr_mux_config'] == 'tristate_feedback': - print(""" + if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p[ + 'iddr_mux_config'] == 'tristate_feedback': + print( + """ wire idelay_{site}; (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *) @@ -258,56 +270,66 @@ def use_direct_and_iddr(p, luts, connects): ) idelay_site_{site} ( .IDATAIN({iwire}), .DATAOUT(idelay_{site}) - );""".format( - **p), file=connects) + );""".format(**p), + file=connects) - print(""" + print( + """ assign {owire} = {onet}; assign {twire} = {tnet}; """.format( onet=luts.get_next_output_net(), tnet=luts.get_next_output_net(), - **p), file=connects) + **p), + file=connects) if p['iddr_mux_config'] == 'direct': - print(''' - assign iddr_d_{site} = {iwire};'''.format( - **p, - ), file=connects) + print( + ''' + assign iddr_d_{site} = {iwire};'''.format(**p, ), + file=connects) elif p['iddr_mux_config'] == 'idelay': - print(''' - assign iddr_d_{site} = idelay_{site};'''.format( - **p, - ), file=connects) + print( + ''' + assign iddr_d_{site} = idelay_{site};'''.format(**p, ), + file=connects) elif p['iddr_mux_config'] == 'tristate_feedback': - print(''' + print( + ''' assign iddr_d_{site} = tfb_{site} ? ofb_{site} : idelay_{site};'''.format( - **p, - ), file=connects) + **p, ), + file=connects) elif p['iddr_mux_config'] == 'none': pass else: assert False, p['mux_config'] if p['mux_config'] == 'direct': - print(''' + print( + ''' assign {net} = {iwire};'''.format( - net=luts.get_next_input_net(), - **p, - ), file=connects) + net=luts.get_next_input_net(), + **p, + ), + file=connects) elif p['mux_config'] == 'idelay': - print(''' + print( + ''' assign {net} = idelay_{site};'''.format( - net=luts.get_next_input_net(), - **p, - ), file=connects) + net=luts.get_next_input_net(), + **p, + ), + file=connects) elif p['mux_config'] == 'none': pass else: assert False, p['mux_config'] + def run(): - iostandards = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'] + iostandards = [ + 'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL' + ] iostandard = random.choice(iostandards) if iostandard in ['LVTTL', 'LVCMOS18']: @@ -330,7 +352,6 @@ def run(): if idx == 0: continue - p = {} p['tile'] = tile p['site'] = site @@ -342,16 +363,17 @@ def run(): p['DRIVE'] = random.choice(drives) p['SLEW'] = verilog.quote(random.choice(slews)) - p['pad_wire'] = 'dio[{}]'.format(idx-1) - p['owire'] = 'do_buf[{}]'.format(idx-1) - p['iwire'] = 'di_buf[{}]'.format(idx-1) - p['twire'] = 't[{}]'.format(idx-1) + p['pad_wire'] = 'dio[{}]'.format(idx - 1) + p['owire'] = 'do_buf[{}]'.format(idx - 1) + p['iwire'] = 'di_buf[{}]'.format(idx - 1) + p['twire'] = 't[{}]'.format(idx - 1) params.append(p) - tile_params.append((tile, site, p['pad_wire'], iostandard, - p['DRIVE'], - verilog.unquote(p['SLEW']) if p['SLEW'] else None, - verilog.unquote(p['PULLTYPE']))) + tile_params.append( + ( + tile, site, p['pad_wire'], iostandard, p['DRIVE'], + verilog.unquote(p['SLEW']) if p['SLEW'] else None, + verilog.unquote(p['PULLTYPE']))) write_params(tile_params) @@ -363,11 +385,11 @@ module top(input clk, inout wire [`N_DI-1:0] dio); wire [`N_DI-1:0] di_buf; wire [`N_DI-1:0] do_buf; wire [`N_DI-1:0] t; - '''.format( - n_di=idx)) + '''.format(n_di=idx)) # Always output a LUT6 to make placer happy. - print(''' + print( + ''' (* KEEP, DONT_TOUCH *) LUT6 dummy_lut(); ''') @@ -375,7 +397,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio); any_idelay = False for p in params: - print(''' + print( + ''' wire iddr_d_{site}; (* KEEP, DONT_TOUCH, LOC = "{site}" *) @@ -387,8 +410,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio); .O({iwire}), .T({twire}) ); - '''.format( - **p), file=connects) + '''.format(**p), + file=connects) p['use_iserdese2'] = random.randint(0, 1) if p['use_iserdese2']: @@ -417,4 +440,3 @@ module top(input clk, inout wire [`N_DI-1:0] dio); if __name__ == '__main__': run() -