mirror of https://github.com/openXC7/prjxray.git
Merge pull request #313 from mcmasterg/clbram_fix
clbram: ignore unexpected LUT contents
This commit is contained in:
John McMaster
GitHub
commit
a2c22c5379
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@ -1,4 +1,4 @@
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N := 1
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N := 2
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SLICEL ?= N
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include ../clb.mk
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@ -2,6 +2,8 @@
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from prjxray.segmaker import Segmaker
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verbose = False
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segmk = Segmaker("design.bits")
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# Can fit 4 per CLB
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@ -16,13 +18,19 @@ multi_bels_bn = [
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'RAM64X1S',
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]
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# Those requiring special resources
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# Just make one per module
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greedy_modules = [
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'my_RAM128X1D',
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'my_RAM128X1S',
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'my_RAM256X1S',
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]
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def load_tcl():
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f = open('design.csv', 'r')
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f.readline()
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ret = {}
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for l in f:
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l = l.strip()
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tile, site, bel, cell, ref_name, prim_type = l.split(',')
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ret[bel] = ref_name
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return ret
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design = load_tcl()
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print("Loading tags")
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'''
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@ -39,9 +47,11 @@ for l in f:
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segmk.add_site_tag(
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loc, "WA7USED",
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module in ('my_RAM128X1D', 'my_RAM128X1S', 'my_RAM256X1S'))
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module in ('my_RAM128X1D', 'my_RAM128X1S_N', 'my_RAM256X1S'))
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segmk.add_site_tag(loc, "WA8USED", module == 'my_RAM256X1S')
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bels_tcl = [design.get("%s/%c6LUT" % (loc, bel), None) for bel in "ABCD"]
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# (a, b, c, d)
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# Size set for RAM32X1S, RAM32X1D, and SRL16E
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size = [0, 0, 0, 0]
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@ -50,9 +60,14 @@ for l in f:
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# RAM set for RAM* primitives
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ram = [0, 0, 0, 0]
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verbose and print('%s' % loc)
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verbose and print(' %s %s %s %s' % tuple(bels_tcl))
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if module == 'my_ram_N':
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# Each one of: SRL16E, SRLC32E, LUT6
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bels = [p0, p1, p2, p3]
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verbose and print(' %s %s %s %s' % tuple(bels))
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assert bels == bels_tcl
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# Clock Enable (CE) clock gate only enabled if we have clocked elements
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# A pure LUT6 does not, but everything else should
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@ -88,14 +103,15 @@ for l in f:
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(0, 0, 1, 1),
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(1, 1, 1, 1),
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]
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has_bel_tcl = tuple([int(bool(x)) for x in bels_tcl])
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# Always use all 4 sites
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if module in ('my_RAM32M', 'my_RAM64M', 'my_RAM128X1D',
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'my_RAM256X1S'):
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ram = [1, 1, 1, 1]
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ram = (1, 1, 1, 1)
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# Only can occupy CD I guess
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elif module == 'my_RAM32X1D':
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ram = [0, 0, 1, 1]
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ram = (0, 0, 1, 1)
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# Uses 2 sites at a time
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elif module in ('my_RAM64X1D_N', 'my_RAM128X1S_N'):
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ram = pack2[n - 1]
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@ -104,8 +120,15 @@ for l in f:
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ram = pack4[n - 1]
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else:
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assert (0)
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verbose and print(' %s %s %s %s' % tuple(ram))
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verbose and print(' %s %s %s %s' % tuple(has_bel_tcl))
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# assert ram == ram_tcl
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# Hack: reject if something unexpected got packed in
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# TODO: place dummy LUTs to exclude placement?
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if ram != has_bel_tcl:
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continue
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# All entries here requiare D
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# All entries here require D
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assert (ram[3])
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if module == 'my_RAM32X1D':
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@ -116,15 +139,17 @@ for l in f:
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size = [1, 1, 1, 1]
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elif module == 'my_RAM32X1S_N':
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size = pack4[n - 1]
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if size != has_bel_tcl:
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continue
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else:
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assert (not module.startswith('my_RAM32'))
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# Now commit bits after marking 1's
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for beli, bel in enumerate('ABCD'):
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segmk.add_site_tag(loc, "%sLUT.RAM" % bel, ram[beli])
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# FIXME: quick fix
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segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli])
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# FIXME
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module == segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
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segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
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def bitfilter(frame_idx, bit_idx):
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@ -1,26 +1,66 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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proc build {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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proc dump {} {
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set roi [get_pblocks roi]
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set fp [open "design.csv" w]
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puts $fp "tile,site,bel,cell,ref_name,prim_type"
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set sites [get_sites -of_objects $roi]
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for {set sitei 0} {$sitei < [llength $sites]} {incr sitei} {
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# set site [get_sites SLICE_X6Y105]
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set site [lindex $sites $sitei]
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set tile [get_tiles -of_objects $site]
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set bels [get_bels -of_objects $site -filter {TYPE == LUT_OR_MEM6}]
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for {set beli 0} {$beli < [llength $bels]} {incr beli} {
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# set bel [get_bels SLICE_X6Y105/D6LUT]
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set bel [lindex $bels $beli]
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set cell [get_cells -of_objects $bel]
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if { "$cell" == "" } {
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continue
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}
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# Ex SRL16E
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set ref_name [get_property REF_NAME $cell]
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# Ex: DMEM.srl.SRL16E
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set prim_type [get_property PRIMITIVE_TYPE $cell]
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puts $fp "$tile,$site,$bel,$cell,$ref_name,$prim_type"
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}
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}
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close $fp
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}
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proc run {} {
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build
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dump
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}
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run
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -58,6 +58,8 @@ for clbi in range(CLBN):
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bel_opts = [
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'SRL16E',
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'SRLC32E',
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# Weight LUT6 more heavily to make WEMUX.CE solve quicker
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'LUT6',
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'LUT6',
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]
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