mirror of https://github.com/openXC7/prjxray.git
John McMaster
GitHub
commit
35d7906251
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@ -0,0 +1,26 @@
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N := 1
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SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_ioblx.db $(addsuffix /segdata_ioblm_[lr].txt,$(SPECIMENS))
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#pushdb:
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# ${XRAY_MERGEDB} ioblm_l build/segbits_ioblx.db
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# ${XRAY_MERGEDB} ioblm_r build/segbits_ioblx.db
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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run:
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$(MAKE) clean
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$(MAKE) database
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$(MAKE) pushdb
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touch run.ok
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clean:
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rm -rf build
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.PHONY: database pushdb run clean
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@ -0,0 +1,4 @@
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# NDI1MUX Fuzzer
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See minitest for DI notes
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@ -0,0 +1,28 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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segmk = Segmaker("design.bits")
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print("Loading tags")
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'''
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port,site,tile,pin,val
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di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
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di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
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'''
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f = open('design.csv', 'r')
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f.readline()
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for l in f:
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l = l.strip()
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port, site, tile, pin, val = l.split(',')
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'''
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PULLTYPE 28 29 30
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NONE X
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KEEPER X X
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PULLDOWN
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PULLUP X X
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'''
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segmk.add_site_tag(site, "PULL.NONE", val in ("NONE", "KEEPER", "PULLUP"))
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segmk.compile()
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segmk.write()
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@ -0,0 +1,5 @@
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#!/bin/bash
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set -ex
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source ${XRAY_DIR}/utils/top_generate.sh
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@ -0,0 +1,102 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc make_io_pin_sites {} {
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# get all possible IOB pins
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foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
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set site [get_sites -of_objects $pad]
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if {[llength $site] == 0} {
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continue
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}
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if [string match IOB33* [get_property SITE_TYPE $site]] {
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dict append io_pin_sites $site $pad
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}
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}
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return $io_pin_sites
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}
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proc load_pin_lines {} {
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# IOB_X0Y103 clk input
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# IOB_X0Y129 do[0] output
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set fp [open "params.csv" r]
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set pin_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend pin_lines [split $line ","]
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}
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close $fp
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return $pin_lines
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}
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proc loc_pins {} {
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set pin_lines [load_pin_lines]
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set io_pin_sites [make_io_pin_sites]
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set fp [open "design.csv" w]
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puts $fp "port,site,tile,pin,val"
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puts "Looping"
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for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
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set line [lindex $pin_lines $idx]
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puts "$line"
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set site_str [lindex $line 0]
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set pin_str [lindex $line 1]
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set io [lindex $line 2]
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set cell_str [lindex $line 3]
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# Have: site
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# Want: pin for site
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set site [get_sites $site_str]
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set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
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# set port [get_ports -of_objects $site]
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set port [get_ports $pin_str]
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set tile [get_tiles -of_objects $site]
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set pin "FIXME"
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set pin [dict get $io_pin_sites $site]
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#set pin [get_property PACKAGE_PIN $port]
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#set cell [get_cells $cell_str]
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# puts "LOCing cell $cell to site $site (from bel $pad_bel)"
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# set_property LOC $site $cell
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port
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# list_property isn't working
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# set keys [list_property_value PULLTYPE $port]
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set keys "PULLUP PULLDOWN KEEPER"
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set val [randsample_list 1 $keys]
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set_property PULLTYPE $val $port
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# puts "IOB $port $site $tile $pin $val"
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puts $fp "$port,$site,$tile,$pin,$val"
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}
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close $fp
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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# Mostly doesn't matter since IOB are special, but add anyway
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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loc_pins
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,147 @@
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'''
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Generate a primitive to place at every I/O
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Unlike CLB tests, the LFSR for this is inside the ROI, not driving it
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'''
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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def gen_iobs():
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'''
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IOB33S: main IOB of a diff pair
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IOB33M: secondary IOB of a diff pair
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IOB33: not a diff pair. Relatively rare (at least in ROI...2 of them?)
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Focus on IOB33S to start
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'''
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for _tile_name, site_name, site_type in util.get_roi().gen_sites(
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#['IOB33', 'IOB33S', 'IOB33M']):
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['IOB33S']):
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yield site_name, site_type
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def write_pins(ports):
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pinstr = ''
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for site, (name, dir_, cell) in sorted(ports.items(), key=lambda x: x[1]):
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# pinstr += 'set_property -dict "PACKAGE_PIN %s IOSTANDARD LVCMOS33" [get_ports %s]' % (packpin, port)
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pinstr += '%s,%s,%s,%s\n' % (site, name, dir_, cell)
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open('params.csv', 'w').write(pinstr)
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def run():
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# All possible values
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iosites = {}
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for site_name, site_type in gen_iobs():
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iosites[site_name] = site_type
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# Assigned in this design
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ports = {}
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DIN_N = 0
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DOUT_N = 0
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def remain_sites():
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return set(iosites.keys()) - set(ports.keys())
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def rand_site():
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'''Get a random, unused site'''
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return random.choice(list(remain_sites()))
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def assign_i(site, name):
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nonlocal DIN_N
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assert site not in ports
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cell = "di_bufs[%u].ibuf" % DIN_N
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DIN_N += 1
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ports[site] = (name, 'input', cell)
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def assign_o(site, name):
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nonlocal DOUT_N
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assert site not in ports
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cell = "do_bufs[%u].obuf" % DOUT_N
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DOUT_N += 1
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ports[site] = (name, 'output', cell)
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# Assign at least one di and one do
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assign_i(rand_site(), 'di[0]')
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assign_o(rand_site(), 'do[0]')
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# Now assign the rest randomly
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while len(remain_sites()):
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if random.randint(0, 1):
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assign_i(rand_site(), 'di[%u]' % DIN_N)
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else:
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assign_o(rand_site(), 'do[%u]' % DOUT_N)
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write_pins(ports)
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print(
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'''
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`define N_DI %u
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`define N_DO %u
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module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do);
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genvar i;
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//Instantiate BUFs so we can LOC them
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wire [`N_DI-1:0] di_buf;
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generate
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for (i = 0; i < `N_DI; i = i+1) begin:di_bufs
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IBUF ibuf(.I(di[i]), .O(di_buf[i]));
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end
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endgenerate
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wire [`N_DO-1:0] do_unbuf;
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generate
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for (i = 0; i < `N_DO; i = i+1) begin:do_bufs
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OBUF obuf(.I(do_unbuf[i]), .O(do[i]));
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end
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endgenerate
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roi roi(.di(di_buf), .do(do_unbuf));
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endmodule
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//Arbitrary terminate into LUTs
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module roi(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do);
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genvar i;
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generate
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for (i = 0; i < `N_DI; i = i+1) begin:dis
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(di[i]),
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.I1(di[i]),
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.I2(di[i]),
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.I3(di[i]),
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.I4(di[i]),
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.I5(di[i]),
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.O());
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end
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endgenerate
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generate
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for (i = 0; i < `N_DO; i = i+1) begin:dos
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(),
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.I1(),
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.I2(),
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.I3(),
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.I4(),
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.I5(),
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.O(do[i]));
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end
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endgenerate
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endmodule
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''' % (DIN_N, DOUT_N))
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if __name__ == '__main__':
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run()
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@ -251,6 +251,18 @@ class Segmaker:
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else:
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assert False, "Invalid name in %s" % site
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def name_y0y1():
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# RAMB18_X0Y41
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m = re.match(r"^(.*)_X.*Y[0-9]*[02468]$", site)
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if m:
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return "%s_Y0" % m.group(1)
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m = re.match(r"^(.*)_X.*Y[0-9]*[13579]$", site)
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if m:
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return "%s_Y1" % m.group(1)
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assert 0, site
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def name_default():
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# most sites are unique within their tile
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# TODO: maybe verify against DB?
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@ -259,6 +271,7 @@ class Segmaker:
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sitekey = {
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'SLICE': name_slice,
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'RAMB18': name_bram18,
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'IOB': name_y0y1,
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}.get(site_prefix, name_default)()
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self.verbose and print(
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'site %s w/ %s prefix => tag %s' %
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Loading…
Reference in New Issue