mirror of https://github.com/openXC7/prjxray.git
clb_ram refinements
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
a3baf1f57c
commit
5c4c5097d4
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@ -40,7 +40,71 @@ module top(input clk, stb, di, output do);
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);
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endmodule
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/*
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Using UG474 recommended primitives
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*/
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module roi(input clk, input [255:0] din, output [255:0] dout);
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my_RAM32X1S #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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my_RAM32X1D #(.LOC("SLICE_X12Y101"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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my_RAM32M #(.LOC("SLICE_X12Y102"))
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c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
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my_RAM64X1S #(.LOC("SLICE_X12Y103"))
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c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
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my_RAM64X1D #(.LOC("SLICE_X12Y104"))
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c4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
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my_RAM64M #(.LOC("SLICE_X12Y105"))
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c5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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my_RAM128X1S #(.LOC("SLICE_X12Y106"))
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c6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8]));
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my_RAM128X1D #(.LOC("SLICE_X12Y107"))
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c7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8]));
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my_RAM256X1S #(.LOC("SLICE_X12Y108"))
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c8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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//Multi-packing
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my_RAM32X1S_2 #(.LOC("SLICE_X12Y110"))
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m0(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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my_RAM32X1S_3 #(.LOC("SLICE_X12Y111"))
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m1(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8]));
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my_RAM32X1S_4 #(.LOC("SLICE_X12Y112"))
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m2(.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 88 +: 8]));
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my_RAM64X1D_2 #(.LOC("SLICE_X12Y113"))
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m3(.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 96 +: 8]));
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//next round
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my_RAM64X1S_2 #(.LOC("SLICE_X12Y114"))
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m4(.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 104 +: 8]));
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my_RAM64X1S_3 #(.LOC("SLICE_X12Y115"))
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m5(.clk(clk), .din(din[ 112 +: 8]), .dout(dout[ 112 +: 8]));
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my_RAM64X1S_4 #(.LOC("SLICE_X12Y116"))
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m6(.clk(clk), .din(din[ 120 +: 8]), .dout(dout[ 120 +: 8]));
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//...and out of bits
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my_RAM128X1S_2 #(.LOC("SLICE_X12Y117"))
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m7(.clk(clk), .din(din[ 200 +: 8]), .dout(dout[ 200 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y100"), .BEL("A6LUT"))
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s0(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y101"), .BEL("B6LUT"))
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s1(.clk(clk), .din(din[ 136 +: 8]), .dout(dout[ 136 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y102"), .BEL("C6LUT"))
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s2(.clk(clk), .din(din[ 144 +: 8]), .dout(dout[ 144 +: 8]));
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my_SRLC32E #(.LOC("SLICE_X14Y103"), .BEL("D6LUT"))
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s3(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y104"), .BEL("A6LUT"))
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s4(.clk(clk), .din(din[ 160 +: 8]), .dout(dout[ 160 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y105"), .BEL("B6LUT"))
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s5(.clk(clk), .din(din[ 168 +: 8]), .dout(dout[ 168 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y106"), .BEL("C6LUT"))
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s6(.clk(clk), .din(din[ 176 +: 8]), .dout(dout[ 176 +: 8]));
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my_SRL16E #(.LOC("SLICE_X14Y107"), .BEL("D6LUT"))
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s7(.clk(clk), .din(din[ 184 +: 8]), .dout(dout[ 184 +: 8]));
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//my_SRL16E_8 #(.LOC("SLICE_X14Y108"))
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// s8(.clk(clk), .din(din[ 192 +: 8]), .dout(dout[ 192 +: 8]));
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endmodule
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module roi_asdfsdf(input clk, input [255:0] din, output [255:0] dout);
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//RAM32X1D 32-Deep by 1-Wide Static Dual Port Synchronous RAM
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my_RAM32X1D #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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@ -76,10 +140,6 @@ module roi_sdffd(input clk, input [255:0] din, output [255:0] dout);
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my_RAM128X1D #(.LOC("SLICE_X12Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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/*
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my_RAM128X1D_2 #(.LOC("SLICE_X12Y101"))
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c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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*/
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/*
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seg SEG_CLBLM_L_X10Y102
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bit 00_40
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bit 01_23
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@ -114,7 +174,7 @@ module roi_sdffd(input clk, input [255:0] din, output [255:0] dout);
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endmodule
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//It created a LUT instead of aggregating using WA7MUX
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module my_RAM64X1S_2 (input clk, input [7:0] din, output [7:0] dout);
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module my_RAM64X1S_2_mux (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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assign dout[0] = din[0] ? oa : ob;
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@ -282,6 +342,33 @@ module my_SRL16E_4 (input clk, input [7:0] din, output [7:0] dout);
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.D(din[6]));
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endmodule
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module my_SRL16E_8 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, BEL="D6LUT" *)
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SRL16E #(
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) lutd2 (
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.Q(dout[7]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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(* LOC=LOC, BEL="D6LUT" *)
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SRL16E #(
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) lutd1 (
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.Q(dout[6]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.CE(din[4]),
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.CLK(din[5]),
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.D(din[6]));
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endmodule
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module my_SRLC32E_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -334,6 +421,79 @@ module my_SRLC32E_4 (input clk, input [7:0] din, output [7:0] dout);
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.D(din[7]));
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endmodule
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module my_RAM32X1S_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM32X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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endmodule
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module my_RAM32X1S_3 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM32X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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(* LOC=LOC *)
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RAM32X1S #(
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) lutb (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.WCLK(din[6]),
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.WE(din[7]));
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endmodule
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module my_RAM32X1S_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -390,6 +550,84 @@ module my_RAM32X1S_4 (input clk, input [7:0] din, output [7:0] dout);
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.WE(din[7]));
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endmodule
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module my_RAM64X1S_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC *)
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RAM64X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X1S_3 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC *)
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RAM64X1S #(
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) lutd (
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.O(dout[3]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC *)
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RAM64X1S #(
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) lutc (
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.O(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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(* LOC=LOC *)
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RAM64X1S #(
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) lutb (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.D(din[6]),
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.WCLK(clk),
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.WE(din[0]));
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endmodule
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module my_RAM64X1S_4 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -1018,40 +1256,6 @@ module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
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.WE(din[2]));
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endmodule
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/*
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hmm?
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CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'roi/c1/lutb/DP.HIGH' at site SLICE_X12Y101,
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Instance roi/c1/lutb/SP.HIGH can not be placed in C6LUT of site SLICE_X12Y101
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because the bel is occupied by roi/c1/luta/SP.HIGH(port:).
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This could be caused by bel constraint conflict
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*/
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module my_RAM128X1D_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM128X1D #(
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.INIT(128'h0),
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.IS_WCLK_INVERTED(1'b0)
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) lutb (
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.DPO(dout[3]),
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.SPO(dout[2]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM128X1D #(
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.INIT(128'h0),
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.IS_WCLK_INVERTED(1'b0)
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) luta (
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.DPO(dout[0]),
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.SPO(dout[1]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]));
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endmodule
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module my_RAM128X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -1071,6 +1275,39 @@ module my_RAM128X1S (input clk, input [7:0] din, output [7:0] dout);
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.WE(din[1]));
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endmodule
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module my_RAM128X1S_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM128X1S #(
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) lutb (
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.O(dout[1]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.A6(din[6]),
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.D(din[7]),
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.WCLK(din[0]),
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.WE(din[1]));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM128X1S #(
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) luta (
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.O(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.A5(din[5]),
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.A6(din[6]),
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.D(din[7]),
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.WCLK(din[0]),
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.WE(din[1]));
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endmodule
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module my_RAM256X1S (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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@ -1129,6 +1366,52 @@ module my_RAM32X1D (input clk, input [7:0] din, output [7:0] dout);
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.WE(din[4]));
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endmodule
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/*
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Invalid
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It tries to place both at D6LUT
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module my_RAM32X1D_2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM32X1D #(
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) lutb (
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.DPO(dout[3]),
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.SPO(dout[2]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.DPRA0(din[6]),
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.DPRA1(din[7]),
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.DPRA2(din[0]),
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.DPRA3(din[1]),
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.DPRA4(din[2]),
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.WCLK(din[3]),
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.WE(din[4]));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM32X1D #(
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) luta (
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.DPO(dout[1]),
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.SPO(dout[0]),
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.A0(din[0]),
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.A1(din[1]),
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.A2(din[2]),
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.A3(din[3]),
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.A4(din[4]),
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.D(din[5]),
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.DPRA0(din[6]),
|
||||
.DPRA1(din[7]),
|
||||
.DPRA2(din[0]),
|
||||
.DPRA3(din[1]),
|
||||
.DPRA4(din[2]),
|
||||
.WCLK(din[3]),
|
||||
.WE(din[4]));
|
||||
endmodule
|
||||
*/
|
||||
|
||||
module my_RAM32X1S (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
parameter BEL="A6LUT";
|
||||
|
|
|
|||
Loading…
Reference in New Issue