mirror of https://github.com/openXC7/prjxray.git
Add documentation for DRAM segbits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Keith Rothman
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DRAM configuration
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==================
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The SLICEM site can turn the 4 LUT6s into distributed RAMs. There are a number of modes, each element is either a 64x1 or a 32x2 distributed RAM (DRAM). The individual elements can be combined into either a 128x1 or 256x1 DRAM.
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Modes
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-----
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Some modes can be enabled at the single LUT level. The following modes are:
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- 32x2 Single port (32x2S)
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- 32x2 Dual port (32x2D)
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- 64x1 Single port (64x1S)
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- 64x1 Dual port (64x1D)
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Some modes are SLICEM wide:
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- 128x1
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- 256x1
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Ports
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-----
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Each LUT element when operating in RAM mode is a DPRAM64.
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+------------+------------+-----------+--------------+
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| Port name | Direction | Width | Description |
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+============+============+===========+==============+
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| WA | IN | 8 | Write address|
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+------------+------------+-----------+--------------+
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| A | IN | 6 | Read address |
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+------------+------------+-----------+--------------+
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| DI | IN | 2 | Data input |
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+------------+------------+-----------+--------------+
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| WE | IN | 1 | Write enable |
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+------------+------------+-----------+--------------+
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| CLK | IN | 1 | Clock |
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+------------+------------+-----------+--------------+
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| O6 | OUT | 1 | Data output 1|
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+------------+------------+-----------+--------------+
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| O5 | OUT | 1 | Data output 2|
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+------------+------------+-----------+--------------+
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Configuration
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=============
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The configuration for the DRAM is found in the following segbits:
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- ALUT.RAM
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- ALUT.SMALL
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- ADI1MUX.AI
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- BLUT.RAM
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- BLUT.SMALL
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- BDI1MUX.BI
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- CLUT.RAM
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- CLUT.SMALL
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- CDI1MUX.CI
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- DLUT.RAM
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- DLUT.SMALL
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- WA7USED
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- WA8USED
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In order to use DRAM in a SLICEM, the DLUT in the SLICEM must be a RAM (e.g. DLUT.RAM).
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In addition the DLUT can never be a dual port RAM because the write address lines for the DLUT are also the read address lines.
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Segbits for modes
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-----------------
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The following table shows the features required for each mode type for each LUT.
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+------+------------+------------+------------+----------+
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| LUTs | 32x2S | 32x2D | 64x1S | 64x1D |
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+------+------------+------------+------------+----------+
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| D | DLUT.RAM | N/A | DLUT.RAM | N/A |
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| | | | | |
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| | DLUT.SMALL | | | |
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+------+------------+------------+------------+----------+
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| C | CLUT.RAM | CLUT.RAM | CLUT.RAM | CLUT.RAM |
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| | | | | |
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| | CLUT.SMALL | CLUT.SMALL | CDI1MUX.CI | |
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| | CDI1MUX.CI | | | |
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+------+------------+------------+------------+----------+
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| B | BLUT.RAM | BLUT.RAM | BLUT.RAM | BLUT.RAM |
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| | | | | |
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| | BLUT.SMALL | BLUT.SMALL | BDI1MUX.CI | |
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| | BDI1MUX.CI | | | |
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+------+------------+------------+------------+----------+
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| A | ALUT.RAM | ALUT.RAM | ALUT.RAM | ALUT.RAM |
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| | | | | |
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| | ALUT.SMALL | ALUT.SMALL | ADI1MUX.CI | |
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| | ADI1MUX.CI | | | |
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+------+------------+------------+------------+----------+
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Ports for modes
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---------------
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In each mode, how the ports are used vary. The following table show the relationship between the LUT mode and ports.
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+------+-------------------------------------+----------------------------+----------------------------------------+-------------------------------+
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| LUTs | 32x2S | 32x2D | 64x1S | 64x1D |
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+------+-------------------------------------+----------------------------+----------------------------------------+-------------------------------+
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| D | WA[4:0] = A[4:0] = {D5,D4,D3,D2,D1} | N/A | WA[5:0] = A[5:0] = {D6,D5,D4,D3,D2,D1} | N/A |
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| | | | | |
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| | DI[1:0] = {DX, DI} | | DI[0] = DI | |
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+------+-------------------------------------+----------------------------+----------------------------------------+-------------------------------+
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| C | WA[4:0] = A[4:0] = {C5,C4,C3,C2,C1} | WA[4:0] = {D5,D4,D3,D2,D1} | WA[5:0] = A[5:0] = {C6,C5,C4,C3,C2,C1} | WA[5:0] = {D6,D5,D4,D3,D2,D1} |
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| | | | | |
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| | DI[1:0] = {CX, CI} | A[4:0] = {C5,C4,C3,C2,C1} | | A[5:0] = {C6,C5,C4,C3,C2,C1} |
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| | | | | |
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| | | DI[1:0] = {CX,DI} | DI[0] = CI | DI[0] = DI |
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+------+-------------------------------------+----------------------------+----------------------------------------+-------------------------------+
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| B | WA[4:0] = A[4:0] = {B5,B4,B3,B2,B1} | WA[4:0] = {D5,D4,D3,D2,D1} | WA[5:0] = A[5:0] = {B6,B5,B4,B3,B2,B1} | WA[5:0] = {D6,D5,D4,D3,D2,D1} |
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| | | | | |
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| | | A[4:0] = {B5,B4,B3,B2,B1} | | A[5:0] = {B6,B5,B4,B3,B2,B1} |
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| | DI[1:0] = {BX, BI} | | DI[0] = BI | |
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| | | DI[1:0] = {BX,DI} | | DI[0] = DI |
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+------+-------------------------------------+----------------------------+----------------------------------------+-------------------------------+
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| A | WA[4:0] = A[4:0] = {A5,A4,A3,A2,A1} | WA[4:0] = {D5,D4,D3,D2,D1} | WA[5:0] = A[5:0] = {A6,A5,A4,A3,A2,A1} | WA[5:0] = {D6,D5,D4,D3,D2,D1} |
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| | | | | |
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| | DI[1:0] = {AX, AI} | A[4:0] = {A5,A4,A3,A2,A1} | DI[0] = AI | A[5:0] = {A6,A5,A4,A3,A2,A1} |
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| | | | | |
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| | | DI[1:0] = {AX,BLUT.DI[0]} | | DI[0] = BLUT.DI[0] |
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+------+-------------------------------------+----------------------------+----------------------------------------+-------------------------------+
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Techlib macros
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--------------
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The tech library exposes the following aggregate modes, which are accomplished with the following combinations.
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+----------+--------------+--------------+--------------+--------------+
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| Macro | Option 1 | Option 2 | Option 3 | Option 4 |
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+----------+--------------+--------------+--------------+--------------+
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| RAM32M | DLUT = 32x2S | | | |
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| | CLUT = 32x2D | | | |
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| | BLUT = 32x2D | | | |
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| | ALUT = 32x2D | | | |
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+----------+--------------+--------------+--------------+--------------+
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| RAM32X1D | DLUT = 32x2S | BLUT = 32x2S | | |
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| | | | | |
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| | CLUT = 32x2D | ALUT = 32x2D | | |
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+----------+--------------+--------------+--------------+--------------+
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| RAM32X1S | DLUT = 32x1S | CLUT = 32x1S | BLUT = 32x1S | ALUT = 32x1S |
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+----------+--------------+--------------+--------------+--------------+
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| RAM32X2S | DLUT = 32x2S | BLUT = 32x2S | | |
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| | CLUT = 32x2D | ALUT = 32x2D | | |
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+----------+--------------+--------------+--------------+--------------+
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| RAM64M | DLUT = 64x1S | | | |
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| | CLUT = 64x1D | | | |
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| | BLUT = 64x1D | | | |
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| | ALUT = 64x1D | | | |
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+----------+--------------+--------------+--------------+--------------+
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| RAM64X1D | DLUT = 64x1S | BLUT = 64x1S | | |
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| | CLUT = 64x1D | ALUT = 64x1D | | |
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+----------+--------------+--------------+--------------+--------------+
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| RAM64X1S | DLUT = 64x1S | CLUT = 64x1S | BLUT = 64x1S | ALUT = 64x1S |
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+----------+--------------+--------------+--------------+--------------+
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