mirror of https://github.com/openXC7/prjxray.git
tilegrid: import KR WIP IOB tcl
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
2a38512720
commit
9537b108d0
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@ -21,6 +21,9 @@ build/clb/deltas:
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build/bram/deltas:
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bash generate.sh build/bram bram
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build/iob/deltas:
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bash generate.sh build/iob iob
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# TODO: only generate addresses
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build/tilegrid.json: build/tilegrid_basic.json
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cd build && python3 ${FUZDIR}/generate_full.py --json-in tilegrid_basic.json --json-out ${BUILD_DIR}/tilegrid.json --tiles $(FUZDIR)/build/tiles/tiles.txt */design_*.delta
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@ -0,0 +1,48 @@
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source "$::env(FUZDIR)/util.tcl"
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# FIXME: change to grab one IOB from each column
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proc loc_iob {} {
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set ports [concat [get_ports clk] [get_ports do] [get_ports stb] [get_ports di]]
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set selected_iobs {}
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foreach port $ports {
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set site [get_sites -of_objects $port]
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set tile [get_tiles -of_objects $site]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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# 50 per column => 50, 100, 150, etc
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if [regexp "Y(?:.*[05])?0" $site] {
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lappend selected_iobs $port
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}
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}
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return $selected_iobs
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}
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proc write_iob { selected_iobs } {
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foreach port $selected_iobs {
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puts ""
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set site [get_sites -of_objects $port]
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set tile [get_tiles -of_objects $site]
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set pin [get_property PACKAGE_PIN $port]
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puts "IOB33 $port $site $tile $pin"
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set orig_init [get_property PULLTYPE $port]
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set_property PULLTYPE PULLUP $port
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write_bitstream -force design_$site.bit
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set_property PULLTYPE "$orig_init" $port
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}
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}
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proc run {} {
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make_project
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set selected_iobs [loc_iob]
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puts "Selected IOBs: [llength $selected_iobs]"
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_iob $selected_iobs
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}
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run
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@ -1,10 +1,19 @@
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//Need at least one LUT per frame base address we want
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`ifndef N_LUT
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`define N_LUT 100
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`define N_BRAM 8
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`endif
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 8;
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localparam integer DOUT_N = `N_LUT + `N_BRAM;
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`ifndef N_BRAM
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`define N_BRAM 8
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`endif
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`ifndef N_DI
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`define N_DI 1
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`endif
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module top(input clk, stb, [DIN_N-1:0] di, output do);
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parameter integer DIN_N = `N_DI;
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parameter integer DOUT_N = `N_LUT + `N_BRAM;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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@ -1,13 +1,61 @@
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proc make_project {} {
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create_project -force -part $::env(XRAY_PART) design design
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proc make_ios {} {
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# get all possible IOB pins
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foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
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set site [get_sites -of_objects $pad]
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if {[llength $site] == 0} {
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continue
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}
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if [string match IOB33* [get_property SITE_TYPE $site]] {
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dict append io_pad_sites $site $pad
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}
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}
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read_verilog "$::env(FUZDIR)/top.v"
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synth_design -top top
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set iopad ""
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dict for {key value} $io_pad_sites {
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lappend iopad [lindex $value 0]
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}
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return $iopad
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}
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proc assign_iobs_old {} {
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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}
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proc assign_iobs {} {
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# Set all I/Os on the bus to valid values somewhere on the chip
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# The iob fuzzer sets these to more specific values
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# All possible IOs
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set iopad [make_ios]
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# Basic pins
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set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb]
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# din bus
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set fixed_pins 3
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set iports [get_ports di*]
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for {set i 0} {$i < [llength $iports]} {incr i} {
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set pad [lindex $iopad [expr $i+$fixed_pins]]
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set port [lindex $iports $i]
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set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
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}
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}
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proc make_project {} {
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# 6 CMTs in our reference part
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# What is the largest?
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set n_di 16
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog "$::env(FUZDIR)/top.v"
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synth_design -top top -verilog_define N_DI=$n_di
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assign_iobs
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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@ -24,4 +72,3 @@ proc make_project {} {
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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}
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