diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile
index 8c487919..7bbfa21a 100644
--- a/fuzzers/005-tilegrid/Makefile
+++ b/fuzzers/005-tilegrid/Makefile
@@ -21,6 +21,9 @@ build/clb/deltas:
 build/bram/deltas:
 	bash generate.sh build/bram bram
 
+build/iob/deltas:
+	bash generate.sh build/iob iob
+
 # TODO: only generate addresses
 build/tilegrid.json: build/tilegrid_basic.json
 	cd build && python3 ${FUZDIR}/generate_full.py --json-in tilegrid_basic.json --json-out ${BUILD_DIR}/tilegrid.json --tiles $(FUZDIR)/build/tiles/tiles.txt */design_*.delta
diff --git a/fuzzers/005-tilegrid/generate_iob.tcl b/fuzzers/005-tilegrid/generate_iob.tcl
new file mode 100644
index 00000000..aa68113d
--- /dev/null
+++ b/fuzzers/005-tilegrid/generate_iob.tcl
@@ -0,0 +1,48 @@
+source "$::env(FUZDIR)/util.tcl"
+
+# FIXME: change to grab one IOB from each column
+proc loc_iob {} {
+    set ports [concat [get_ports clk] [get_ports do] [get_ports stb] [get_ports di]]
+    set selected_iobs {}
+    foreach port $ports {
+        set site [get_sites -of_objects $port]
+        set tile [get_tiles -of_objects $site]
+        set grid_x [get_property GRID_POINT_X $tile]
+        set grid_y [get_property GRID_POINT_Y $tile]
+         # 50 per column => 50, 100, 150, etc
+        if [regexp "Y(?:.*[05])?0" $site] {
+            lappend selected_iobs $port
+        }
+    }
+    return $selected_iobs
+}
+
+proc write_iob { selected_iobs } {
+    foreach port $selected_iobs {
+      puts ""
+      set site [get_sites -of_objects $port]
+      set tile [get_tiles -of_objects $site]
+      set pin [get_property PACKAGE_PIN $port]
+      puts "IOB33 $port $site $tile $pin"
+      set orig_init [get_property PULLTYPE $port]
+      set_property PULLTYPE PULLUP $port
+      write_bitstream -force design_$site.bit
+      set_property PULLTYPE "$orig_init" $port
+    }
+}
+
+proc run {} {
+    make_project
+    set selected_iobs [loc_iob]
+    puts "Selected IOBs: [llength $selected_iobs]"
+
+    place_design
+    route_design
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+
+    write_iob $selected_iobs
+}
+
+run
+
diff --git a/fuzzers/005-tilegrid/top.v b/fuzzers/005-tilegrid/top.v
index 55edc442..0d321e3f 100644
--- a/fuzzers/005-tilegrid/top.v
+++ b/fuzzers/005-tilegrid/top.v
@@ -1,10 +1,19 @@
 //Need at least one LUT per frame base address we want
+`ifndef N_LUT
 `define N_LUT 100
-`define N_BRAM 8
+`endif
 
-module top(input clk, stb, di, output do);
-	localparam integer DIN_N = 8;
-	localparam integer DOUT_N = `N_LUT + `N_BRAM;
+`ifndef N_BRAM
+`define N_BRAM 8
+`endif
+
+`ifndef N_DI
+`define N_DI 1
+`endif
+
+module top(input clk, stb, [DIN_N-1:0] di, output do);
+	parameter integer DIN_N = `N_DI;
+	parameter integer DOUT_N = `N_LUT + `N_BRAM;
 
 	reg [DIN_N-1:0] din;
 	wire [DOUT_N-1:0] dout;
diff --git a/fuzzers/005-tilegrid/util.tcl b/fuzzers/005-tilegrid/util.tcl
index ce56cf7b..0ef61a14 100644
--- a/fuzzers/005-tilegrid/util.tcl
+++ b/fuzzers/005-tilegrid/util.tcl
@@ -1,13 +1,61 @@
-proc make_project {} {
-    create_project -force -part $::env(XRAY_PART) design design
+proc make_ios {} {
+    # get all possible IOB pins
+    foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
+        set site [get_sites -of_objects $pad]
+        if {[llength $site] == 0} {
+           continue
+        }
+        if [string match IOB33* [get_property SITE_TYPE $site]] {
+            dict append io_pad_sites $site $pad
+        }
+    }
 
-    read_verilog "$::env(FUZDIR)/top.v"
-    synth_design -top top
+    set iopad ""
+    dict for {key value} $io_pad_sites {
+        lappend iopad [lindex $value 0]
+    }
+    return $iopad
+}
 
+proc assign_iobs_old {} {
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
+}
+
+proc assign_iobs {} {
+    # Set all I/Os on the bus to valid values somewhere on the chip
+    # The iob fuzzer sets these to more specific values
+
+    # All possible IOs
+    set iopad [make_ios]
+    # Basic pins
+    set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb]
+
+    # din bus
+    set fixed_pins 3
+    set iports [get_ports di*]
+    for {set i 0} {$i < [llength $iports]} {incr i} {
+      set pad [lindex $iopad [expr $i+$fixed_pins]]
+      set port [lindex $iports $i]
+      set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port
+    }
+}
+
+proc make_project {} {
+    # 6 CMTs in our reference part
+    # What is the largest?
+    set n_di 16
+
+    create_project -force -part $::env(XRAY_PART) design design
+
+    read_verilog "$::env(FUZDIR)/top.v"
+    synth_design -top top -verilog_define N_DI=$n_di
+
+    assign_iobs
 
     create_pblock roi
     add_cells_to_pblock [get_pblocks roi] [get_cells roi]
@@ -24,4 +72,3 @@ proc make_project {} {
     set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 }
 
-