mirror of https://github.com/openXC7/prjxray.git
timfuz: placelut as standalone data generator
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
5d8d0b22d8
commit
943ab5bbb7
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@ -1,22 +0,0 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all: $(SPECIMENS_OK)
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#python timfuz.py specimen_*/timing.txt
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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run:
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$(MAKE) clean
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$(MAKE) all
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touch run.ok
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits __pycache__ run.ok
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rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
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.PHONY: database pushdb run clean
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@ -1,9 +0,0 @@
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#!/bin/bash
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set -ex
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source ${XRAY_GENHEADER}
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python ../placelut_ff_fb.py --sdx 4 --sdy 4 >placelut.v
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vivado -mode batch -source ../generate.tcl
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@ -1,279 +0,0 @@
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source ../../../utils/utils.tcl
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proc pin_info {pin} {
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set cell [get_cells -of_objects $pin]
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set bel [get_bels -of_objects $cell]
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set site [get_sites -of_objects $bel]
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return "$site $bel"
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}
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proc pin_bel {pin} {
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set cell [get_cells -of_objects $pin]
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set bel [get_bels -of_objects $cell]
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return $bel
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}
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proc build_design {} {
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create_project -force -part $::env(XRAY_PART) design design
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#read_verilog ../top.v
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#read_verilog ../picorv32.v
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#read_verilog ../oneblinkw.v
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read_verilog placelut.v
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synth_design -top top
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puts "Locking pins"
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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puts "Package stuff"
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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if {0 < 0} {
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puts "pblocking"
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create_pblock roi
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set roipb [get_pblocks roi]
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set_property EXCLUDE_PLACEMENT 1 $roipb
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add_cells_to_pblock $roipb [get_cells roi]
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resize_pblock $roipb -add "$::env(XRAY_ROI)"
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puts "randplace"
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randplace_pblock 150 $roipb
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}
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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puts "dedicated route"
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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# disable combinitorial loop
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# set_property IS_ENABLED 0 [get_drc_checks {LUTLP-1}]
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#write_bitstream -force design.bit
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}
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# Changed to group wires and nodes
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# This allows tracing the full path along with pips
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proc write_info3 {} {
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set outdir "."
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set fp [open "$outdir/timing3.txt" w]
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# bel as site/bel, so don't bother with site
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puts $fp "net src_bel dst_bel ico fast_max fast_min slow_max slow_min pips inodes wires"
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set TIME_start [clock clicks -milliseconds]
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set verbose 0
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set equations 0
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set site_src_nets 0
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set site_dst_nets 0
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set neti 0
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set nets [get_nets -hierarchical]
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set nnets [llength $nets]
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foreach net $nets {
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incr neti
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#if {$neti >= 10} {
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# puts "Debug break"
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# break
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#}
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puts "Net $neti / $nnets: $net"
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# The semantics of get_pins -leaf is kind of odd
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# When no passthrough LUTs exist, it has no effect
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# When passthrough LUT present:
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# -w/o -leaf: some pins + passthrough LUT pins
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# -w/ -leaf: different pins + passthrough LUT pins
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# With OUT filter this seems to be sufficient
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set src_pin [get_pins -leaf -filter {DIRECTION == OUT} -of_objects $net]
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set src_bel [pin_bel $src_pin]
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set src_site [get_sites -of_objects $src_bel]
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# Only one net driver
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set src_site_pins [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]
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# Sometimes this is empty for reasons that escape me
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# Emitting direction doesn't help
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if {[llength $src_site_pins] < 1} {
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if $verbose {
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puts " Ignoring site internal net"
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}
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incr site_src_nets
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continue
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}
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set dst_site_pins_net [get_site_pins -filter {DIRECTION == IN} -of_objects $net]
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if {[llength $dst_site_pins_net] < 1} {
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puts " Skipping site internal source net"
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incr site_dst_nets
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continue
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}
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foreach src_site_pin $src_site_pins {
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if $verbose {
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puts "Source: $src_pin at site $src_site:$src_bel, spin $src_site_pin"
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}
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# Run with and without interconnect only
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foreach ico "0 1" {
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set ico_flag ""
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if $ico {
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set ico_flag "-interconnect_only"
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set delays [get_net_delays $ico_flag -of_objects $net]
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} else {
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set delays [get_net_delays -of_objects $net]
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}
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foreach delay $delays {
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set delaystr [get_property NAME $delay]
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set dst_pins [get_property TO_PIN $delay]
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set dst_pin [get_pins $dst_pins]
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#puts " $delaystr: $src_pin => $dst_pin"
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set dst_bel [pin_bel $dst_pin]
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set dst_site [get_sites -of_objects $dst_bel]
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if $verbose {
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puts " Dest: $dst_pin at site $dst_site:$dst_bel"
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}
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set dst_site_pins [get_site_pins -of_objects $dst_pin]
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# Some nets are internal
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# But should this happen on dest if we've already filtered source?
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if {"$dst_site_pins" eq ""} {
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continue
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}
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# Also apparantly you can have multiple of these as well
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foreach dst_site_pin $dst_site_pins {
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set fast_max [get_property "FAST_MAX" $delay]
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set fast_min [get_property "FAST_MIN" $delay]
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set slow_max [get_property "SLOW_MAX" $delay]
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set slow_min [get_property "SLOW_MIN" $delay]
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# Want:
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# Site / BEL at src
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# Site / BEL at dst
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# Pips in between
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# Walk net, looking for interesting elements in between
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set pips [get_pips -of_objects $net -from $src_site_pin -to $dst_site_pin]
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if $verbose {
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foreach pip $pips {
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puts " PIP $pip"
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}
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}
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set nodes [get_nodes -of_objects $net -from $src_site_pin -to $dst_site_pin]
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#set wires [get_wires -of_objects $net -from $src_site_pin -to $dst_site_pin]
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set wires [get_wires -of_objects $nodes]
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# puts $fp "$net $src_bel $dst_bel $ico $fast_max $fast_min $slow_max $slow_min $pips"
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puts -nonewline $fp "$net $src_bel $dst_bel $ico $fast_max $fast_min $slow_max $slow_min"
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# Write pips w/ speed index
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puts -nonewline $fp " "
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set needspace 0
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foreach pip $pips {
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if $needspace {
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puts -nonewline $fp "|"
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}
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set speed_index [get_property SPEED_INDEX $pip]
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puts -nonewline $fp "$pip:$speed_index"
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set needspace 1
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}
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# Write nodes
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#set nodes_str [string map {" " "|"} $nodes]
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#puts -nonewline $fp " $nodes_str"
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puts -nonewline $fp " "
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set needspace 0
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foreach node $nodes {
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if $needspace {
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puts -nonewline $fp "|"
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}
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set nwires [llength [get_wires -of_objects $node]]
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puts -nonewline $fp "$node:$nwires"
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set needspace 1
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}
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# Write wires
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puts -nonewline $fp " "
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set needspace 0
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foreach wire $wires {
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if $needspace {
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puts -nonewline $fp "|"
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}
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set speed_index [get_property SPEED_INDEX $wire]
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puts -nonewline $fp "$wire:$speed_index"
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set needspace 1
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}
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puts $fp ""
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incr equations
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break
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}
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}
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}
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}
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}
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close $fp
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set TIME_taken [expr [clock clicks -milliseconds] - $TIME_start]
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puts "Took ms: $TIME_taken"
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puts "Generated $equations equations"
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puts "Skipped $site_src_nets (+ $site_dst_nets) site nets"
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}
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proc pips_all {} {
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set outdir "."
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set fp [open "$outdir/pip_all.txt" w]
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set items [get_pips]
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puts "Items: [llength $items]"
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set needspace 0
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set properties [list_property [lindex $items 0]]
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foreach item $items {
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set needspace 0
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foreach property $properties {
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set val [get_property $property $item]
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if {"$val" ne ""} {
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if $needspace {
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puts -nonewline $fp " "
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}
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puts -nonewline $fp "$property:$val"
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set needspace 1
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}
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}
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puts $fp ""
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}
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close $fp
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}
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proc wires_all {} {
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set outdir "."
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set fp [open "$outdir/wire_all.txt" w]
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set items [get_wires]
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puts "Items: [llength $items]"
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set needspace 0
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set properties [list_property [lindex $items 0]]
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foreach item $items {
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set needspace 0
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foreach property $properties {
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set val [get_property $property $item]
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if {"$val" ne ""} {
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if $needspace {
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puts -nonewline $fp " "
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}
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puts -nonewline $fp "$property:$val"
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set needspace 1
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}
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}
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puts $fp ""
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}
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close $fp
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}
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build_design
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#write_info2
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write_info3
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#wires_all
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#pips_all
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@ -0,0 +1,52 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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CSVS := $(addsuffix /timing3.csv,$(SPECIMENS))
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TIMFUZ_DIR=$(XRAY_DIR)/fuzzers/007-timing
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all: tilea.json
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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run:
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$(MAKE) clean
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$(MAKE) all
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touch run.ok
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits __pycache__ run.ok
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rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
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rm -rf build
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.PHONY: database pushdb run clean
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sub.json: $(SPECIMENS_OK)
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# Discover which variables can be separated
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# This is typically the longest running operation
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python3 $(TIMFUZ_DIR)/rref.py --simplify --out sub.json $(CSVS)
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grouped.csv: $(SPECIMENS_OK) sub.json
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# Separate variables
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python3 $(TIMFUZ_DIR)/csv_flat2group.py --sub-json sub.json --strict $(CSVS) grouped.csv
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# Verify sub.json makes a solvable solution
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# python3 $(TIMFUZ_DIR)/checksub.py --sub-json sub.json grouped.csv
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leastsq.csv: sub.json grouped.csv
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# Create a rough timing model that approximately fits the given paths
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python3 $(TIMFUZ_DIR)/solve_leastsq.py --sub-json sub.json grouped.csv --out leastsq.csv
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linprog.csv: leastsq.csv grouped.csv
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# Tweak rough timing model, making sure all constraints are satisfied
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python3 $(TIMFUZ_DIR)/solve_linprog.py --sub-json sub.json --sub-csv leastsq.csv --massage grouped.csv --out linprog.csv
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flat.csv: linprog.csv
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# Take separated variables and back-annotate them to the original timing variables
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python3 $(TIMFUZ_DIR)/csv_group2flat.py --sub-json sub.json --sort linprog.csv flat.csv
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tilea.json: flat.csv
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# Final processing
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# Insert timing delays into actual tile layouts
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python3 $(TIMFUZ_DIR)/tile_annotate.py --tile-json $(TIMFUZ_DIR)/timgrid/build/timgrid.json flat.csv tilea.json
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@ -25,7 +25,7 @@ nlut = 4 * SDX * SDY
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nin = 6 * nlut
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nout = nlut
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print('placelut simple')
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print('//placelut simple')
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print('//SBASE: %s' % (SBASE,))
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print('//SDX: %s' % (SDX,))
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print('//SDY: %s' % (SDX,))
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@ -0,0 +1,11 @@
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#!/bin/bash
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set -ex
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source ${XRAY_GENHEADER}
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TIMFUZ_DIR=$XRAY_DIR/fuzzers/007-timing
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python ../generate.py --sdx 4 --sdy 4 >top.v
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vivado -mode batch -source ../generate.tcl
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python3 $TIMFUZ_DIR/timing_txt2csv.py --speed-json $TIMFUZ_DIR/speed/build/speed.json --out timing3.csv timing3.txt
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@ -0,0 +1,47 @@
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source ../../../../../utils/utils.tcl
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source ../../project.tcl
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proc build_design {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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puts "Locking pins"
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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puts "Package stuff"
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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puts "pblocking"
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create_pblock roi
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set roipb [get_pblocks roi]
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set_property EXCLUDE_PLACEMENT 1 $roipb
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add_cells_to_pblock $roipb [get_cells roi]
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resize_pblock $roipb -add "$::env(XRAY_ROI)"
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puts "randplace"
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randplace_pblock 50 roi
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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puts "dedicated route"
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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|
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place_design
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route_design
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||||
|
||||
write_checkpoint -force design.dcp
|
||||
# disable combinitorial loop
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||||
# set_property IS_ENABLED 0 [get_drc_checks {LUTLP-1}]
|
||||
#write_bitstream -force design.bit
|
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}
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build_design
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write_info3
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|
|
@ -1,8 +0,0 @@
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#!/usr/bin/env bash
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set -ex
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mkdir -p build_speed
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cd build_speed
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vivado -mode batch -source ../speed.tcl
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python ../speed_json.py speed_model.txt node.txt speed.json
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@ -0,0 +1,2 @@
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build
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@ -0,0 +1,12 @@
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all: build/speed.json
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build/node.txt: speed_json.py generate.tcl
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mkdir -p build
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cd build && vivado -mode batch -source ../generate.tcl
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|
||||
build/speed.json: build/node.txt
|
||||
cd build && python ../speed_json.py speed_model.txt node.txt speed.json
|
||||
|
||||
clean:
|
||||
rm -rf build
|
||||
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
Generates speed.json, describing speed index to string translation.
|
||||
These indices appear to be fixed between runtimes.
|
||||
It is unknown how stable they are across versions.
|
||||
|
||||
|
|
@ -1,5 +1,3 @@
|
|||
source ../../../utils/utils.tcl
|
||||
|
||||
proc pin_info {pin} {
|
||||
set cell [get_cells -of_objects $pin]
|
||||
set bel [get_bels -of_objects $cell]
|
||||
|
|
@ -16,24 +14,17 @@ proc pin_bel {pin} {
|
|||
proc build_design_full {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog ../top.v
|
||||
read_verilog ../picorv32.v
|
||||
read_verilog ../../src/picorv32.v
|
||||
synth_design -top top
|
||||
|
||||
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
#set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
|
||||
# [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
|
||||
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
|
||||
|
||||
create_pblock roi
|
||||
set roipb [get_pblocks roi]
|
||||
set_property EXCLUDE_PLACEMENT 1 $roipb
|
||||
add_cells_to_pblock $roipb [get_cells roi]
|
||||
resize_pblock $roipb -add "$::env(XRAY_ROI)"
|
||||
|
||||
randplace_pblock 150 $roipb
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
|
@ -145,7 +136,7 @@ proc nodes_unique_cc {} {
|
|||
set outdir "."
|
||||
set fp [open "$outdir/node.txt" w]
|
||||
set items [get_nodes]
|
||||
puts "Items: [llength $items]"
|
||||
puts "Computing cost codes with [llength $items] items"
|
||||
|
||||
set needspace 0
|
||||
set properties [list_property [lindex $items 0]]
|
||||
|
|
@ -157,7 +148,7 @@ proc nodes_unique_cc {} {
|
|||
if {[ dict exists $cost_codes_known $cost_code ]} {
|
||||
continue
|
||||
}
|
||||
puts "Adding $cost_code @ item $itemi"
|
||||
puts " Adding cost code $cost_code @ item $itemi"
|
||||
dict set cost_codes_known $cost_code 1
|
||||
|
||||
set needspace 0
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
module top(input clk, stb, di, output do);
|
||||
reg dor;
|
||||
always @(posedge clk) begin
|
||||
dor <= stb & di;
|
||||
end
|
||||
assign do = dor;
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
build
|
||||
|
|
@ -1,26 +1,12 @@
|
|||
all: build/timgrid.json
|
||||
|
||||
N := 1
|
||||
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
|
||||
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
|
||||
build/timgrid.txt: generate.tcl
|
||||
mkdir -p build
|
||||
cd build && vivado -mode batch -source ../generate.tcl
|
||||
|
||||
database: $(SPECIMENS_OK)
|
||||
cp specimen_001/tilegrid.json tilegrid.json
|
||||
|
||||
pushdb:
|
||||
cp tilegrid.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tilegrid.json
|
||||
|
||||
$(SPECIMENS_OK):
|
||||
bash generate.sh $(subst /OK,,$@)
|
||||
touch $@
|
||||
|
||||
run:
|
||||
$(MAKE) clean
|
||||
$(MAKE) database
|
||||
$(MAKE) pushdb
|
||||
touch run.ok
|
||||
build/timgrid.json: build/timgrid.txt
|
||||
cd build && python3 ../tile_txt2json.py --speed-json ../../speed/build/speed.json timgrid.txt timgrid.json
|
||||
|
||||
clean:
|
||||
rm -rf specimen_[0-9][0-9][0-9]/ tilegrid.json run.ok
|
||||
|
||||
.PHONY: database pushdb clean run
|
||||
rm -rf build
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
proc create_project {} {
|
||||
proc build_project {} {
|
||||
if 0 {
|
||||
set grid_min_x -1
|
||||
set grid_max_x -1
|
||||
|
|
@ -83,7 +83,7 @@ proc write_data {} {
|
|||
set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
|
||||
|
||||
# Write tiles.txt with site metadata
|
||||
set fp [open "tiles.txt" w]
|
||||
set fp [open "timgrid.txt" w]
|
||||
foreach tile $tiles {
|
||||
set type [get_property TYPE $tile]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
|
|
@ -114,6 +114,6 @@ proc write_data {} {
|
|||
close $fp
|
||||
}
|
||||
|
||||
create_project
|
||||
build_project
|
||||
write_data
|
||||
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ def main():
|
|||
description=
|
||||
'Solve timing solution'
|
||||
)
|
||||
parser.add_argument('--speed-json', default='build_speed/speed.json',
|
||||
parser.add_argument('--speed-json', default='../../speed/build/speed.json',
|
||||
help='Provides speed index to name translation')
|
||||
parser.add_argument('fnin', default=None, help='input tcl output .txt')
|
||||
parser.add_argument('fnout', default=None, help='output .json')
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from timfuz import Benchmark, row_di2ds, A_di2ds
|
||||
from timfuz import Benchmark, A_di2ds
|
||||
import numpy as np
|
||||
import glob
|
||||
import math
|
||||
Loading…
Reference in New Issue