diff --git a/fuzzers/007-timing/Makefile b/fuzzers/007-timing/Makefile
deleted file mode 100644
index 8da96c3f..00000000
--- a/fuzzers/007-timing/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-N := 1
-SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
-SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
-
-all: $(SPECIMENS_OK)
-	#python timfuz.py specimen_*/timing.txt
-
-$(SPECIMENS_OK):
-	bash generate.sh $(subst /OK,,$@)
-	touch $@
-
-run:
-	$(MAKE) clean
-	$(MAKE) all
-	touch run.ok
-
-clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits __pycache__ run.ok
-	rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
-
-.PHONY: database pushdb run clean
-
diff --git a/fuzzers/007-timing/generate.sh b/fuzzers/007-timing/generate.sh
deleted file mode 100755
index eebd0388..00000000
--- a/fuzzers/007-timing/generate.sh
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-source ${XRAY_GENHEADER}
-
-python ../placelut_ff_fb.py --sdx 4 --sdy 4  >placelut.v
-vivado -mode batch -source ../generate.tcl
-
diff --git a/fuzzers/007-timing/generate.tcl b/fuzzers/007-timing/generate.tcl
deleted file mode 100644
index a2e76c71..00000000
--- a/fuzzers/007-timing/generate.tcl
+++ /dev/null
@@ -1,279 +0,0 @@
-source ../../../utils/utils.tcl
-
-proc pin_info {pin} {
-    set cell [get_cells -of_objects $pin]
-    set bel [get_bels -of_objects $cell]
-    set site [get_sites -of_objects $bel]
-    return "$site $bel"
-}
-
-proc pin_bel {pin} {
-    set cell [get_cells -of_objects $pin]
-    set bel [get_bels -of_objects $cell]
-    return $bel
-}
-
-proc build_design {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    #read_verilog ../top.v
-    #read_verilog ../picorv32.v
-    #read_verilog ../oneblinkw.v
-    read_verilog placelut.v
-    synth_design -top top
-
-    puts "Locking pins"
-    set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
-		[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
-
-    puts "Package stuff"
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
-
-    if {0 < 0} {
-        puts "pblocking"
-        create_pblock roi
-        set roipb [get_pblocks roi]
-        set_property EXCLUDE_PLACEMENT 1 $roipb
-        add_cells_to_pblock $roipb [get_cells roi]
-        resize_pblock $roipb -add "$::env(XRAY_ROI)"
-
-        puts "randplace"
-        randplace_pblock 150 $roipb
-    }
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    puts "dedicated route"
-    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
-
-    place_design
-
-    
-    route_design
-
-    write_checkpoint -force design.dcp
-    # disable combinitorial loop
-    # set_property IS_ENABLED 0 [get_drc_checks {LUTLP-1}]
-    #write_bitstream -force design.bit
-}
-
-# Changed to group wires and nodes
-# This allows tracing the full path along with pips
-proc write_info3 {} {
-    set outdir "."
-    set fp [open "$outdir/timing3.txt" w]
-    # bel as site/bel, so don't bother with site
-    puts $fp "net src_bel dst_bel ico fast_max fast_min slow_max slow_min pips inodes wires"
-
-    set TIME_start [clock clicks -milliseconds]
-    set verbose 0
-    set equations 0
-    set site_src_nets 0
-    set site_dst_nets 0
-    set neti 0
-    set nets [get_nets -hierarchical]
-    set nnets [llength $nets]
-    foreach net $nets {
-        incr neti
-        #if {$neti >= 10} {
-        #    puts "Debug break"
-        #    break
-        #}
-
-        puts "Net $neti / $nnets: $net"
-        # The semantics of get_pins -leaf is kind of odd
-        # When no passthrough LUTs exist, it has no effect
-        # When passthrough LUT present:
-        # -w/o -leaf: some pins + passthrough LUT pins
-        # -w/ -leaf: different pins + passthrough LUT pins
-        # With OUT filter this seems to be sufficient
-        set src_pin [get_pins -leaf -filter {DIRECTION == OUT} -of_objects $net]
-        set src_bel [pin_bel $src_pin]
-        set src_site [get_sites -of_objects $src_bel]
-        # Only one net driver
-        set src_site_pins [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]
-
-        # Sometimes this is empty for reasons that escape me
-        # Emitting direction doesn't help
-        if {[llength $src_site_pins] < 1} {
-            if $verbose {
-                puts "    Ignoring site internal net"
-            }
-            incr site_src_nets
-            continue
-        }
-        set dst_site_pins_net [get_site_pins -filter {DIRECTION == IN} -of_objects $net]
-        if {[llength $dst_site_pins_net] < 1} {
-            puts "  Skipping site internal source net"
-            incr site_dst_nets
-            continue
-        }
-        foreach src_site_pin $src_site_pins {
-            if $verbose {
-                puts "Source: $src_pin at site $src_site:$src_bel, spin $src_site_pin"
-            }
-
-            # Run with and without interconnect only
-            foreach ico "0 1" {
-                set ico_flag ""
-                if $ico {
-                    set ico_flag "-interconnect_only"
-                    set delays [get_net_delays $ico_flag -of_objects $net]
-                } else {
-                    set delays [get_net_delays -of_objects $net]
-                }
-                foreach delay $delays {
-                    set delaystr [get_property NAME $delay]
-                    set dst_pins [get_property TO_PIN $delay]
-                    set dst_pin [get_pins $dst_pins]
-                    #puts "  $delaystr: $src_pin => $dst_pin"
-                    set dst_bel [pin_bel $dst_pin]
-                    set dst_site [get_sites -of_objects $dst_bel]
-                    if $verbose {
-                        puts "  Dest: $dst_pin at site $dst_site:$dst_bel"
-                    }
-
-                    set dst_site_pins [get_site_pins -of_objects $dst_pin]
-                    # Some nets are internal
-                    # But should this happen on dest if we've already filtered source?
-                    if {"$dst_site_pins" eq ""} {
-                        continue
-                    }
-                    # Also apparantly you can have multiple of these as well
-                    foreach dst_site_pin $dst_site_pins {
-                        set fast_max [get_property "FAST_MAX" $delay]
-                        set fast_min [get_property "FAST_MIN" $delay]
-                        set slow_max [get_property "SLOW_MAX" $delay]
-                        set slow_min [get_property "SLOW_MIN" $delay]
-
-                        # Want:
-                        # Site / BEL at src
-                        # Site / BEL at dst
-                        # Pips in between
-                        # Walk net, looking for interesting elements in between
-                        set pips [get_pips -of_objects $net -from $src_site_pin -to $dst_site_pin]
-                        if $verbose {
-                            foreach pip $pips {
-                                puts "    PIP $pip"
-                            }
-                        }
-                        set nodes [get_nodes -of_objects $net -from $src_site_pin -to $dst_site_pin]
-                        #set wires [get_wires -of_objects $net -from $src_site_pin -to $dst_site_pin]
-                        set wires [get_wires -of_objects $nodes]
-
-                        # puts $fp "$net $src_bel $dst_bel $ico $fast_max $fast_min $slow_max $slow_min $pips"
-                        puts -nonewline $fp "$net $src_bel $dst_bel $ico $fast_max $fast_min $slow_max $slow_min"
-        
-                        # Write pips w/ speed index
-                        puts -nonewline $fp " "
-                        set needspace 0
-                        foreach pip $pips {
-                            if $needspace {
-                                puts -nonewline $fp "|"
-                            }
-                            set speed_index [get_property SPEED_INDEX $pip]
-                            puts -nonewline $fp "$pip:$speed_index"
-                            set needspace 1
-                        }
-
-                        # Write nodes
-                        #set nodes_str [string map {" " "|"} $nodes]
-                        #puts -nonewline $fp " $nodes_str"
-                        puts -nonewline $fp " "
-                        set needspace 0
-                        foreach node $nodes {
-                            if $needspace {
-                                puts -nonewline $fp "|"
-                            }
-                            set nwires [llength [get_wires -of_objects $node]]
-                            puts -nonewline $fp "$node:$nwires"
-                            set needspace 1
-                        }
-
-                        # Write wires
-                        puts -nonewline $fp " "
-                        set needspace 0
-                        foreach wire $wires {
-                            if $needspace {
-                                puts -nonewline $fp "|"
-                            }
-                            set speed_index [get_property SPEED_INDEX $wire]
-                            puts -nonewline $fp "$wire:$speed_index"
-                            set needspace 1
-                        }
-
-                        puts $fp ""
-
-                        incr equations
-                        break
-                    }
-                }
-            }
-        }
-    }
-    close $fp
-    set TIME_taken [expr [clock clicks -milliseconds] - $TIME_start]
-    puts "Took ms: $TIME_taken"
-    puts "Generated $equations equations"
-    puts "Skipped $site_src_nets (+ $site_dst_nets) site nets"
-}
-
-proc pips_all {} {
-    set outdir "."
-    set fp [open "$outdir/pip_all.txt" w]
-    set items [get_pips]
-    puts "Items: [llength $items]"
-
-    set needspace 0
-    set properties [list_property [lindex $items 0]]
-    foreach item $items {
-        set needspace 0
-        foreach property $properties {
-            set val [get_property $property $item]
-            if {"$val" ne ""} {
-                if $needspace {
-                    puts -nonewline $fp " "
-                }
-                puts -nonewline $fp "$property:$val"
-                set needspace 1
-            }
-        }
-        puts $fp ""
-    }
-    close $fp
-}
-proc wires_all {} {
-    set outdir "."
-    set fp [open "$outdir/wire_all.txt" w]
-    set items [get_wires]
-    puts "Items: [llength $items]"
-
-    set needspace 0
-    set properties [list_property [lindex $items 0]]
-    foreach item $items {
-        set needspace 0
-        foreach property $properties {
-            set val [get_property $property $item]
-            if {"$val" ne ""} {
-                if $needspace {
-                    puts -nonewline $fp " "
-                }
-                puts -nonewline $fp "$property:$val"
-                set needspace 1
-            }
-        }
-        puts $fp ""
-    }
-    close $fp
-}
-
-build_design
-#write_info2
-write_info3
-#wires_all
-#pips_all
-
diff --git a/fuzzers/007-timing/oneblinkw.v b/fuzzers/007-timing/projects/oneblinkw/oneblinkw.v
similarity index 100%
rename from fuzzers/007-timing/oneblinkw.v
rename to fuzzers/007-timing/projects/oneblinkw/oneblinkw.v
diff --git a/fuzzers/007-timing/top.v b/fuzzers/007-timing/projects/picorv32/top.v
similarity index 100%
rename from fuzzers/007-timing/top.v
rename to fuzzers/007-timing/projects/picorv32/top.v
diff --git a/fuzzers/007-timing/projects/placelut/Makefile b/fuzzers/007-timing/projects/placelut/Makefile
new file mode 100644
index 00000000..df00e979
--- /dev/null
+++ b/fuzzers/007-timing/projects/placelut/Makefile
@@ -0,0 +1,52 @@
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+CSVS := $(addsuffix /timing3.csv,$(SPECIMENS))
+TIMFUZ_DIR=$(XRAY_DIR)/fuzzers/007-timing
+
+all: tilea.json
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+run:
+	$(MAKE) clean
+	$(MAKE) all
+	touch run.ok
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits __pycache__ run.ok
+	rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
+	rm -rf build
+
+.PHONY: database pushdb run clean
+
+sub.json: $(SPECIMENS_OK)
+	# Discover which variables can be separated
+	# This is typically the longest running operation
+	python3 $(TIMFUZ_DIR)/rref.py --simplify --out sub.json $(CSVS)
+
+grouped.csv: $(SPECIMENS_OK) sub.json
+	# Separate variables
+	python3 $(TIMFUZ_DIR)/csv_flat2group.py --sub-json sub.json --strict $(CSVS) grouped.csv
+	# Verify sub.json makes a solvable solution
+	# python3 $(TIMFUZ_DIR)/checksub.py --sub-json sub.json grouped.csv
+
+leastsq.csv: sub.json grouped.csv
+	# Create a rough timing model that approximately fits the given paths
+	python3 $(TIMFUZ_DIR)/solve_leastsq.py --sub-json sub.json grouped.csv --out leastsq.csv
+
+linprog.csv: leastsq.csv grouped.csv
+	# Tweak rough timing model, making sure all constraints are satisfied
+	python3 $(TIMFUZ_DIR)/solve_linprog.py --sub-json sub.json --sub-csv leastsq.csv --massage grouped.csv --out linprog.csv
+
+flat.csv: linprog.csv
+	# Take separated variables and back-annotate them to the original timing variables
+	python3 $(TIMFUZ_DIR)/csv_group2flat.py --sub-json sub.json --sort linprog.csv flat.csv
+
+tilea.json: flat.csv
+	# Final processing
+	# Insert timing delays into actual tile layouts
+	python3 $(TIMFUZ_DIR)/tile_annotate.py --tile-json $(TIMFUZ_DIR)/timgrid/build/timgrid.json flat.csv tilea.json
+
diff --git a/fuzzers/007-timing/placelut.py b/fuzzers/007-timing/projects/placelut/generate.py
similarity index 98%
rename from fuzzers/007-timing/placelut.py
rename to fuzzers/007-timing/projects/placelut/generate.py
index 47dd9e3c..a56d4c55 100644
--- a/fuzzers/007-timing/placelut.py
+++ b/fuzzers/007-timing/projects/placelut/generate.py
@@ -25,7 +25,7 @@ nlut = 4 * SDX * SDY
 nin = 6 * nlut
 nout = nlut
 
-print('placelut simple')
+print('//placelut simple')
 print('//SBASE: %s' % (SBASE,))
 print('//SDX: %s' % (SDX,))
 print('//SDY: %s' % (SDX,))
diff --git a/fuzzers/007-timing/projects/placelut/generate.sh b/fuzzers/007-timing/projects/placelut/generate.sh
new file mode 100755
index 00000000..fff71d31
--- /dev/null
+++ b/fuzzers/007-timing/projects/placelut/generate.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+set -ex
+
+source ${XRAY_GENHEADER}
+TIMFUZ_DIR=$XRAY_DIR/fuzzers/007-timing
+
+python ../generate.py --sdx 4 --sdy 4  >top.v
+vivado -mode batch -source ../generate.tcl
+python3 $TIMFUZ_DIR/timing_txt2csv.py --speed-json $TIMFUZ_DIR/speed/build/speed.json --out timing3.csv timing3.txt
+
diff --git a/fuzzers/007-timing/projects/placelut/generate.tcl b/fuzzers/007-timing/projects/placelut/generate.tcl
new file mode 100644
index 00000000..0b536169
--- /dev/null
+++ b/fuzzers/007-timing/projects/placelut/generate.tcl
@@ -0,0 +1,47 @@
+source ../../../../../utils/utils.tcl
+source ../../project.tcl
+
+proc build_design {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    puts "Locking pins"
+    set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
+		[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
+
+    puts "Package stuff"
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+    puts "pblocking"
+    create_pblock roi
+    set roipb [get_pblocks roi]
+    set_property EXCLUDE_PLACEMENT 1 $roipb
+    add_cells_to_pblock $roipb [get_cells roi]
+    resize_pblock $roipb -add "$::env(XRAY_ROI)"
+
+    puts "randplace"
+    randplace_pblock 50 roi
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    puts "dedicated route"
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    # disable combinitorial loop
+    # set_property IS_ENABLED 0 [get_drc_checks {LUTLP-1}]
+    #write_bitstream -force design.bit
+}
+
+build_design
+write_info3
+
diff --git a/fuzzers/007-timing/placelut_fb.py b/fuzzers/007-timing/projects/placelut_fb/placelut_fb.py
similarity index 100%
rename from fuzzers/007-timing/placelut_fb.py
rename to fuzzers/007-timing/projects/placelut_fb/placelut_fb.py
diff --git a/fuzzers/007-timing/placelut_ff_fb.py b/fuzzers/007-timing/projects/placelut_ff_fb/placelut_ff_fb.py
similarity index 100%
rename from fuzzers/007-timing/placelut_ff_fb.py
rename to fuzzers/007-timing/projects/placelut_ff_fb/placelut_ff_fb.py
diff --git a/fuzzers/007-timing/speed.sh b/fuzzers/007-timing/speed.sh
deleted file mode 100755
index 0712c64f..00000000
--- a/fuzzers/007-timing/speed.sh
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/usr/bin/env bash
-set -ex
-
-mkdir -p build_speed
-cd build_speed
-vivado -mode batch -source ../speed.tcl
-python ../speed_json.py speed_model.txt node.txt speed.json
-
diff --git a/fuzzers/007-timing/speed/.gitignore b/fuzzers/007-timing/speed/.gitignore
new file mode 100644
index 00000000..9ef96044
--- /dev/null
+++ b/fuzzers/007-timing/speed/.gitignore
@@ -0,0 +1,2 @@
+build
+
diff --git a/fuzzers/007-timing/speed/Makefile b/fuzzers/007-timing/speed/Makefile
new file mode 100644
index 00000000..e2b7a520
--- /dev/null
+++ b/fuzzers/007-timing/speed/Makefile
@@ -0,0 +1,12 @@
+all: build/speed.json
+
+build/node.txt: speed_json.py generate.tcl
+	mkdir -p build
+	cd build && vivado -mode batch -source ../generate.tcl
+
+build/speed.json: build/node.txt
+	cd build && python ../speed_json.py speed_model.txt node.txt speed.json
+
+clean:
+	rm -rf build
+
diff --git a/fuzzers/007-timing/speed/README.md b/fuzzers/007-timing/speed/README.md
new file mode 100644
index 00000000..a10f335d
--- /dev/null
+++ b/fuzzers/007-timing/speed/README.md
@@ -0,0 +1,4 @@
+Generates speed.json, describing speed index to string translation.
+These indices appear to be fixed between runtimes.
+It is unknown how stable they are across versions.
+
diff --git a/fuzzers/007-timing/speed.tcl b/fuzzers/007-timing/speed/generate.tcl
similarity index 90%
rename from fuzzers/007-timing/speed.tcl
rename to fuzzers/007-timing/speed/generate.tcl
index 31f8b857..cf423e65 100644
--- a/fuzzers/007-timing/speed.tcl
+++ b/fuzzers/007-timing/speed/generate.tcl
@@ -1,5 +1,3 @@
-source ../../../utils/utils.tcl
-
 proc pin_info {pin} {
     set cell [get_cells -of_objects $pin]
     set bel [get_bels -of_objects $cell]
@@ -16,24 +14,17 @@ proc pin_bel {pin} {
 proc build_design_full {} {
     create_project -force -part $::env(XRAY_PART) design design
     read_verilog ../top.v
-    read_verilog ../picorv32.v
+    read_verilog ../../src/picorv32.v
     synth_design -top top
 
-    set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
-		[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
+    #set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
+	#	[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
 
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
     set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
 
-    create_pblock roi
-    set roipb [get_pblocks roi]
-    set_property EXCLUDE_PLACEMENT 1 $roipb
-    add_cells_to_pblock $roipb [get_cells roi]
-    resize_pblock $roipb -add "$::env(XRAY_ROI)"
-
-    randplace_pblock 150 $roipb
     set_property CFGBVS VCCO [current_design]
     set_property CONFIG_VOLTAGE 3.3 [current_design]
     set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
@@ -145,7 +136,7 @@ proc nodes_unique_cc {} {
     set outdir "."
     set fp [open "$outdir/node.txt" w]
     set items [get_nodes]
-    puts "Items: [llength $items]"
+    puts "Computing cost codes with [llength $items] items"
 
     set needspace 0
     set properties [list_property [lindex $items 0]]
@@ -157,7 +148,7 @@ proc nodes_unique_cc {} {
         if {[ dict exists $cost_codes_known $cost_code ]} {
             continue
         }
-        puts "Adding $cost_code @ item $itemi"
+        puts "  Adding cost code $cost_code @ item $itemi"
         dict set cost_codes_known $cost_code 1
 
         set needspace 0
diff --git a/fuzzers/007-timing/speed_json.py b/fuzzers/007-timing/speed/speed_json.py
similarity index 100%
rename from fuzzers/007-timing/speed_json.py
rename to fuzzers/007-timing/speed/speed_json.py
diff --git a/fuzzers/007-timing/speed/top.v b/fuzzers/007-timing/speed/top.v
new file mode 100644
index 00000000..cf662548
--- /dev/null
+++ b/fuzzers/007-timing/speed/top.v
@@ -0,0 +1,8 @@
+module top(input clk, stb, di, output do);
+    reg dor;
+	always @(posedge clk) begin
+	    dor <= stb & di;
+	end
+    assign do = dor;
+endmodule
+
diff --git a/fuzzers/007-timing/picorv32.v b/fuzzers/007-timing/src/picorv32.v
similarity index 100%
rename from fuzzers/007-timing/picorv32.v
rename to fuzzers/007-timing/src/picorv32.v
diff --git a/fuzzers/007-timing/timgrid/.gitignore b/fuzzers/007-timing/timgrid/.gitignore
new file mode 100644
index 00000000..378eac25
--- /dev/null
+++ b/fuzzers/007-timing/timgrid/.gitignore
@@ -0,0 +1 @@
+build
diff --git a/fuzzers/007-timing/timgrid/Makefile b/fuzzers/007-timing/timgrid/Makefile
index c59f83bf..af0a72da 100644
--- a/fuzzers/007-timing/timgrid/Makefile
+++ b/fuzzers/007-timing/timgrid/Makefile
@@ -1,26 +1,12 @@
+all: build/timgrid.json
 
-N := 1
-SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
-SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+build/timgrid.txt: generate.tcl
+	mkdir -p build
+	cd build && vivado -mode batch -source ../generate.tcl
 
-database: $(SPECIMENS_OK)
-	cp specimen_001/tilegrid.json tilegrid.json
-
-pushdb:
-	cp tilegrid.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tilegrid.json
-
-$(SPECIMENS_OK):
-	bash generate.sh $(subst /OK,,$@)
-	touch $@
-
-run:
-	$(MAKE) clean
-	$(MAKE) database
-	$(MAKE) pushdb
-	touch run.ok
+build/timgrid.json: build/timgrid.txt
+	cd build && python3 ../tile_txt2json.py --speed-json ../../speed/build/speed.json timgrid.txt timgrid.json
 
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ tilegrid.json run.ok
-
-.PHONY: database pushdb clean run
+	rm -rf build
 
diff --git a/fuzzers/007-timing/timgrid/generate.tcl b/fuzzers/007-timing/timgrid/generate.tcl
index 70a9b030..c7f218bc 100644
--- a/fuzzers/007-timing/timgrid/generate.tcl
+++ b/fuzzers/007-timing/timgrid/generate.tcl
@@ -1,4 +1,4 @@
-proc create_project {} {
+proc build_project {} {
     if 0 {
         set grid_min_x -1
         set grid_max_x -1
@@ -83,7 +83,7 @@ proc write_data {} {
     set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
 
     # Write tiles.txt with site metadata
-    set fp [open "tiles.txt" w]
+    set fp [open "timgrid.txt" w]
     foreach tile $tiles {
 	    set type [get_property TYPE $tile]
 	    set grid_x [get_property GRID_POINT_X $tile]
@@ -114,6 +114,6 @@ proc write_data {} {
     close $fp
 }
 
-create_project
+build_project
 write_data
 
diff --git a/fuzzers/007-timing/tile_txt2json.py b/fuzzers/007-timing/timgrid/tile_txt2json.py
similarity index 96%
rename from fuzzers/007-timing/tile_txt2json.py
rename to fuzzers/007-timing/timgrid/tile_txt2json.py
index 06711f87..b6e410ff 100644
--- a/fuzzers/007-timing/tile_txt2json.py
+++ b/fuzzers/007-timing/timgrid/tile_txt2json.py
@@ -62,7 +62,7 @@ def main():
         description=
         'Solve timing solution'
     )
-    parser.add_argument('--speed-json', default='build_speed/speed.json',
+    parser.add_argument('--speed-json', default='../../speed/build/speed.json',
         help='Provides speed index to name translation')
     parser.add_argument('fnin', default=None, help='input tcl output .txt')
     parser.add_argument('fnout', default=None, help='output .json')
diff --git a/fuzzers/007-timing/timfuz_csv.py b/fuzzers/007-timing/timing_txt2csv.py
similarity index 99%
rename from fuzzers/007-timing/timfuz_csv.py
rename to fuzzers/007-timing/timing_txt2csv.py
index 97da40e1..51f04f42 100644
--- a/fuzzers/007-timing/timfuz_csv.py
+++ b/fuzzers/007-timing/timing_txt2csv.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-from timfuz import Benchmark, row_di2ds, A_di2ds
+from timfuz import Benchmark, A_di2ds
 import numpy as np
 import glob
 import math