mirror of https://github.com/openXC7/prjxray.git
Add some CARRY4 related tests to "simple" experiment
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf
parent
e91686fdd7
commit
916cae0ccd
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@ -10,6 +10,7 @@
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/hd_visual/
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/vivado[_.]*
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/usage_statistics_webtalk.*
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/lutlist.txt
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/lutdata.txt
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/carrydata.txt
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/segdata.txt
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/database.txt
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@ -1,25 +0,0 @@
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# set carry_cell [lindex [get_cells -hierarchical -filter {REF_NAME == CARRY4}] 0]
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proc get_carry_cyinit_mux_cfg {carry_cell} {
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set cyinit_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == CYINIT}]
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set cyinit_net [get_nets -quiet -of_objects $cyinit_pin]
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if {[string last "<const0>" $cyinit_net] > 0} { return "zero" }
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if {[string last "<const1>" $cyinit_net] > 0} { return "one" }
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set cin_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CIN]
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set cin_net [get_nets -quiet -of_objects $cin_pin]
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if {"$cyinit_net" == "$cin_net"} { return "cin" }
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$cyinit_net" == "$ax_net"} { return "ax" }
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return "unknown"
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}
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proc list_carry_cyinit_mux_cfg {} {
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foreach carry_cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] {
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puts "[get_bels -of_objects $carry_cell] [get_carry_cyinit_mux_cfg $carry_cell]"
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}
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}
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@ -28,6 +28,7 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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EOT
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cat > design.tcl << EOT
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source "utilities.tcl"
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create_project -force -part $XRAY_PART design design
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read_xdc design.xdc
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@ -41,16 +42,28 @@ route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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puts "Writing lutlist.txt."
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set fp [open "lutlist.txt" w]
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set luts [get_cells -hierarchical -filter {REF_NAME == LUT6}]
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foreach lut \$luts {
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set bel [get_property BEL \$lut]
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set loc [get_property LOC \$lut]
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set init [get_property INIT \$lut]
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puts "Writing lutdata.txt."
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set fp [open "lutdata.txt" w]
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foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
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set bel [get_property BEL \$cell]
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set loc [get_property LOC \$cell]
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set init [get_property INIT \$cell]
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puts \$fp "\$loc \$bel \$init"
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}
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close \$fp
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puts "Writing carrydata.txt."
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set fp [open "carrydata.txt" w]
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foreach cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] {
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set loc [get_property LOC \$cell]
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set cyinit_mux [get_carry_cyinit_mux_cfg \$cell]
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set di0_mux [get_carry_di0_mux_cfg \$cell]
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set di1_mux [get_carry_di1_mux_cfg \$cell]
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set di2_mux [get_carry_di2_mux_cfg \$cell]
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set di3_mux [get_carry_di3_mux_cfg \$cell]
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puts \$fp "\$loc \$cyinit_mux \$di0_mux \$di1_mux \$di2_mux \$di3_mux"
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}
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close \$fp
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EOT
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rm -rf design design.log
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@ -8,6 +8,7 @@ import os, json, re
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grid = None
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bits = dict()
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luts = dict()
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carry = dict()
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print("Loading grid.")
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with open("../gridinfo/grid-%s-db.json" % os.getenv("XRAY_PART"), "r") as f:
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@ -30,8 +31,8 @@ with open("design.bits", "r") as f:
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bits[base_frame][bit_wordidx].add((bit_frame, bit_wordidx, bit_bitidx))
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print("Loading luts.")
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with open("lutlist.txt", "r") as f:
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print("Loading lut data.")
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with open("lutdata.txt", "r") as f:
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for line in f:
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line = line.split()
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site = line[0]
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@ -45,6 +46,17 @@ with open("lutlist.txt", "r") as f:
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bitname = "%s.INIT[%02d]" % (bel, i)
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luts[site][bitname] = ((init >> i) & 1) != 0
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print("Loading carry data.")
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with open("carrydata.txt", "r") as f:
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for line in f:
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line = line.split()
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assert line[0] not in carry
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carry[line[0]] = dict()
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for i, n in enumerate("CYINIT:ZRO:ONE:AX:CIN DI0:AX:O5 DI1:AX:O5 DI2:AX:O5 DI3:AX:O5".split()):
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n = n.split(":")
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for k in n[1:]:
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carry[line[0]]["CARRY_%s_MUX_%s" % (n[0], k)] = line[1+i].upper() == k
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#################################################
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# Group per Segment
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@ -68,7 +80,7 @@ for tilename, tiledata in grid["tiles"].items():
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segments[segname] = { "bits": list(), "tags": dict() }
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for site in tiledata["sites"]:
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if site not in luts:
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if site not in luts and site not in carry:
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continue
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if re.match(r"SLICE_X[0-9]*[02468]Y", site):
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@ -78,14 +90,20 @@ for tilename, tiledata in grid["tiles"].items():
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else:
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assert 0
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for name, value in luts[site].items():
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tile_type = tiledata["props"]["TYPE"]
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if site in luts:
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for name, value in luts[site].items():
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tile_type = tiledata["props"]["TYPE"]
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# LUT init bits are in the same position for all CLBL[LM]_[LR] tiles
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if re.match("^CLBL[LM]_[LR]", tile_type) and "LUT.INIT" in name:
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tile_type = "CLBLX_X"
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# LUT init bits are in the same position for all CLBL[LM]_[LR] tiles
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if re.match("^CLBL[LM]_[LR]", tile_type) and "LUT.INIT" in name:
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tile_type = "CLBLX_X"
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segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value
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segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value
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if site in carry:
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for name, value in carry[site].items():
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tile_type = tiledata["props"]["TYPE"]
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segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value
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base_frame = int(tiledata["cfgcol"]["BASE_FRAMEID"][2:], 16)
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for wordidx in tiledata["cfgcol"]["WORDS"]:
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@ -0,0 +1,76 @@
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proc puts_list {l} {
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foreach e $l {puts $e}
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}
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proc get_carry_cyinit_mux_cfg {carry_cell} {
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set cyinit_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == CYINIT}]
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set cyinit_net [get_nets -quiet -of_objects $cyinit_pin]
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if {[string last "<const0>" $cyinit_net] > 0} { return "zro" }
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if {[string last "<const1>" $cyinit_net] > 0} { return "one" }
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$cyinit_net" == "$ax_net"} { return "ax " }
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set cin_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CIN]
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set cin_net [get_nets -quiet -of_objects $cin_pin]
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if {"$cyinit_net" == "$cin_net"} { return "cin" }
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return "???"
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}
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proc get_carry_di0_mux_cfg {carry_cell} {
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set di0_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[0]}]
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set di0_net [get_nets -quiet -of_objects $di0_pin]
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set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX]
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set ax_net [get_nets -quiet -of_objects $ax_pin]
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if {"$di0_net" == "$ax_net"} { return "ax " }
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return "o5 "
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}
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proc get_carry_di1_mux_cfg {carry_cell} {
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set di1_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[1]}]
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set di1_net [get_nets -quiet -of_objects $di1_pin]
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set bx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */BX]
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set bx_net [get_nets -quiet -of_objects $bx_pin]
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if {"$di1_net" == "$bx_net"} { return "bx " }
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return "o5 "
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}
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proc get_carry_di2_mux_cfg {carry_cell} {
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set di2_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[2]}]
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set di2_net [get_nets -quiet -of_objects $di2_pin]
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set cx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CX]
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set cx_net [get_nets -quiet -of_objects $cx_pin]
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if {"$di2_net" == "$cx_net"} { return "cx " }
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return "o5 "
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}
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proc get_carry_di3_mux_cfg {carry_cell} {
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set di3_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[3]}]
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set di3_net [get_nets -quiet -of_objects $di3_pin]
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set dx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */DX]
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set dx_net [get_nets -quiet -of_objects $dx_pin]
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if {"$di3_net" == "$dx_net"} { return "dx " }
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return "o5 "
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}
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proc list_carry_cfg {} {
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foreach carry_cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] {
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set cyinit_mux_cfg [get_carry_cyinit_mux_cfg $carry_cell]
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set di0_mux_cfg [get_carry_di0_mux_cfg $carry_cell]
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set di1_mux_cfg [get_carry_di1_mux_cfg $carry_cell]
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set di2_mux_cfg [get_carry_di2_mux_cfg $carry_cell]
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set di3_mux_cfg [get_carry_di3_mux_cfg $carry_cell]
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puts "[get_bels -of_objects $carry_cell] $cyinit_mux_cfg $di0_mux_cfg $di1_mux_cfg $di2_mux_cfg $di3_mux_cfg"
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}
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}
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@ -194,8 +194,6 @@ help:
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} else {
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printf(" <%d candidates>\n", num_candidates);
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}
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assert(num_candidates != 0);
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}
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return 0;
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