From 916cae0ccd1de2949d36306e4f77cf791db466c4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 13 Oct 2017 22:00:49 +0200 Subject: [PATCH] Add some CARRY4 related tests to "simple" experiment Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- simple/.gitignore | 3 +- simple/carry_cyinit_mux.tcl | 25 ------------ simple/runme.sh | 27 +++++++++---- simple/segdata.py | 36 +++++++++++++----- simple/utilities.tcl | 76 +++++++++++++++++++++++++++++++++++++ tools/segmatch.cc | 2 - 6 files changed, 125 insertions(+), 44 deletions(-) delete mode 100644 simple/carry_cyinit_mux.tcl create mode 100644 simple/utilities.tcl diff --git a/simple/.gitignore b/simple/.gitignore index 4fbc6e9c..729092a8 100644 --- a/simple/.gitignore +++ b/simple/.gitignore @@ -10,6 +10,7 @@ /hd_visual/ /vivado[_.]* /usage_statistics_webtalk.* -/lutlist.txt +/lutdata.txt +/carrydata.txt /segdata.txt /database.txt diff --git a/simple/carry_cyinit_mux.tcl b/simple/carry_cyinit_mux.tcl deleted file mode 100644 index 8d0d92e6..00000000 --- a/simple/carry_cyinit_mux.tcl +++ /dev/null @@ -1,25 +0,0 @@ -# set carry_cell [lindex [get_cells -hierarchical -filter {REF_NAME == CARRY4}] 0] - -proc get_carry_cyinit_mux_cfg {carry_cell} { - set cyinit_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == CYINIT}] - set cyinit_net [get_nets -quiet -of_objects $cyinit_pin] - - if {[string last "" $cyinit_net] > 0} { return "zero" } - if {[string last "" $cyinit_net] > 0} { return "one" } - - set cin_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CIN] - set cin_net [get_nets -quiet -of_objects $cin_pin] - if {"$cyinit_net" == "$cin_net"} { return "cin" } - - set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX] - set ax_net [get_nets -quiet -of_objects $ax_pin] - if {"$cyinit_net" == "$ax_net"} { return "ax" } - - return "unknown" -} - -proc list_carry_cyinit_mux_cfg {} { - foreach carry_cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] { - puts "[get_bels -of_objects $carry_cell] [get_carry_cyinit_mux_cfg $carry_cell]" - } -} diff --git a/simple/runme.sh b/simple/runme.sh index 4cafba54..465b37b7 100644 --- a/simple/runme.sh +++ b/simple/runme.sh @@ -28,6 +28,7 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] EOT cat > design.tcl << EOT +source "utilities.tcl" create_project -force -part $XRAY_PART design design read_xdc design.xdc @@ -41,16 +42,28 @@ route_design write_checkpoint -force design.dcp write_bitstream -force design.bit -puts "Writing lutlist.txt." -set fp [open "lutlist.txt" w] -set luts [get_cells -hierarchical -filter {REF_NAME == LUT6}] -foreach lut \$luts { - set bel [get_property BEL \$lut] - set loc [get_property LOC \$lut] - set init [get_property INIT \$lut] +puts "Writing lutdata.txt." +set fp [open "lutdata.txt" w] +foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] { + set bel [get_property BEL \$cell] + set loc [get_property LOC \$cell] + set init [get_property INIT \$cell] puts \$fp "\$loc \$bel \$init" } close \$fp + +puts "Writing carrydata.txt." +set fp [open "carrydata.txt" w] +foreach cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] { + set loc [get_property LOC \$cell] + set cyinit_mux [get_carry_cyinit_mux_cfg \$cell] + set di0_mux [get_carry_di0_mux_cfg \$cell] + set di1_mux [get_carry_di1_mux_cfg \$cell] + set di2_mux [get_carry_di2_mux_cfg \$cell] + set di3_mux [get_carry_di3_mux_cfg \$cell] + puts \$fp "\$loc \$cyinit_mux \$di0_mux \$di1_mux \$di2_mux \$di3_mux" +} +close \$fp EOT rm -rf design design.log diff --git a/simple/segdata.py b/simple/segdata.py index b5894980..2d29a117 100644 --- a/simple/segdata.py +++ b/simple/segdata.py @@ -8,6 +8,7 @@ import os, json, re grid = None bits = dict() luts = dict() +carry = dict() print("Loading grid.") with open("../gridinfo/grid-%s-db.json" % os.getenv("XRAY_PART"), "r") as f: @@ -30,8 +31,8 @@ with open("design.bits", "r") as f: bits[base_frame][bit_wordidx].add((bit_frame, bit_wordidx, bit_bitidx)) -print("Loading luts.") -with open("lutlist.txt", "r") as f: +print("Loading lut data.") +with open("lutdata.txt", "r") as f: for line in f: line = line.split() site = line[0] @@ -45,6 +46,17 @@ with open("lutlist.txt", "r") as f: bitname = "%s.INIT[%02d]" % (bel, i) luts[site][bitname] = ((init >> i) & 1) != 0 +print("Loading carry data.") +with open("carrydata.txt", "r") as f: + for line in f: + line = line.split() + assert line[0] not in carry + carry[line[0]] = dict() + for i, n in enumerate("CYINIT:ZRO:ONE:AX:CIN DI0:AX:O5 DI1:AX:O5 DI2:AX:O5 DI3:AX:O5".split()): + n = n.split(":") + for k in n[1:]: + carry[line[0]]["CARRY_%s_MUX_%s" % (n[0], k)] = line[1+i].upper() == k + ################################################# # Group per Segment @@ -68,7 +80,7 @@ for tilename, tiledata in grid["tiles"].items(): segments[segname] = { "bits": list(), "tags": dict() } for site in tiledata["sites"]: - if site not in luts: + if site not in luts and site not in carry: continue if re.match(r"SLICE_X[0-9]*[02468]Y", site): @@ -78,14 +90,20 @@ for tilename, tiledata in grid["tiles"].items(): else: assert 0 - for name, value in luts[site].items(): - tile_type = tiledata["props"]["TYPE"] + if site in luts: + for name, value in luts[site].items(): + tile_type = tiledata["props"]["TYPE"] - # LUT init bits are in the same position for all CLBL[LM]_[LR] tiles - if re.match("^CLBL[LM]_[LR]", tile_type) and "LUT.INIT" in name: - tile_type = "CLBLX_X" + # LUT init bits are in the same position for all CLBL[LM]_[LR] tiles + if re.match("^CLBL[LM]_[LR]", tile_type) and "LUT.INIT" in name: + tile_type = "CLBLX_X" - segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value + segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value + + if site in carry: + for name, value in carry[site].items(): + tile_type = tiledata["props"]["TYPE"] + segments[segname]["tags"]["%s.%s.%s" % (tile_type, sitekey, name)] = value base_frame = int(tiledata["cfgcol"]["BASE_FRAMEID"][2:], 16) for wordidx in tiledata["cfgcol"]["WORDS"]: diff --git a/simple/utilities.tcl b/simple/utilities.tcl new file mode 100644 index 00000000..ed55f164 --- /dev/null +++ b/simple/utilities.tcl @@ -0,0 +1,76 @@ +proc puts_list {l} { + foreach e $l {puts $e} +} + +proc get_carry_cyinit_mux_cfg {carry_cell} { + set cyinit_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == CYINIT}] + set cyinit_net [get_nets -quiet -of_objects $cyinit_pin] + + if {[string last "" $cyinit_net] > 0} { return "zro" } + if {[string last "" $cyinit_net] > 0} { return "one" } + + set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX] + set ax_net [get_nets -quiet -of_objects $ax_pin] + if {"$cyinit_net" == "$ax_net"} { return "ax " } + + set cin_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CIN] + set cin_net [get_nets -quiet -of_objects $cin_pin] + if {"$cyinit_net" == "$cin_net"} { return "cin" } + + return "???" +} + +proc get_carry_di0_mux_cfg {carry_cell} { + set di0_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[0]}] + set di0_net [get_nets -quiet -of_objects $di0_pin] + + set ax_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */AX] + set ax_net [get_nets -quiet -of_objects $ax_pin] + if {"$di0_net" == "$ax_net"} { return "ax " } + + return "o5 " +} + +proc get_carry_di1_mux_cfg {carry_cell} { + set di1_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[1]}] + set di1_net [get_nets -quiet -of_objects $di1_pin] + + set bx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */BX] + set bx_net [get_nets -quiet -of_objects $bx_pin] + if {"$di1_net" == "$bx_net"} { return "bx " } + + return "o5 " +} + +proc get_carry_di2_mux_cfg {carry_cell} { + set di2_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[2]}] + set di2_net [get_nets -quiet -of_objects $di2_pin] + + set cx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */CX] + set cx_net [get_nets -quiet -of_objects $cx_pin] + if {"$di2_net" == "$cx_net"} { return "cx " } + + return "o5 " +} + +proc get_carry_di3_mux_cfg {carry_cell} { + set di3_pin [get_pins -of_objects $carry_cell -filter {REF_PIN_NAME == DI[3]}] + set di3_net [get_nets -quiet -of_objects $di3_pin] + + set dx_pin [get_site_pins -of_objects [get_sites -of_objects $carry_cell] */DX] + set dx_net [get_nets -quiet -of_objects $dx_pin] + if {"$di3_net" == "$dx_net"} { return "dx " } + + return "o5 " +} + +proc list_carry_cfg {} { + foreach carry_cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] { + set cyinit_mux_cfg [get_carry_cyinit_mux_cfg $carry_cell] + set di0_mux_cfg [get_carry_di0_mux_cfg $carry_cell] + set di1_mux_cfg [get_carry_di1_mux_cfg $carry_cell] + set di2_mux_cfg [get_carry_di2_mux_cfg $carry_cell] + set di3_mux_cfg [get_carry_di3_mux_cfg $carry_cell] + puts "[get_bels -of_objects $carry_cell] $cyinit_mux_cfg $di0_mux_cfg $di1_mux_cfg $di2_mux_cfg $di3_mux_cfg" + } +} diff --git a/tools/segmatch.cc b/tools/segmatch.cc index d4645698..cc6c4513 100644 --- a/tools/segmatch.cc +++ b/tools/segmatch.cc @@ -194,8 +194,6 @@ help: } else { printf(" <%d candidates>\n", num_candidates); } - - assert(num_candidates != 0); } return 0;