Add fixedpnr minitests

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

minitests/fixedpnr/.gitignore

@@ -0,0 +1,8 @@
+/.Xil/
+/design_fd?e/
+/design_fd?e.dcp
+/design_fd?e.bit
+/design_fd?e.bits
+/fixed.xdc
+/usage_statistics_webtalk.*
+/vivado*

minitests/fixedpnr/runme.sh

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+#!/bin/bash
+
+set -ex
+vivado -mode batch -source runme.tcl
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_fdre.bits -z -y design_fdre.bit
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_fdse.bits -z -y design_fdse.bit
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_fdce.bits -z -y design_fdce.bit
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_fdpe.bits -z -y design_fdpe.bit
+diff -u design_fdre.bits design_fdse.bits

minitests/fixedpnr/runme.tcl

@@ -0,0 +1,46 @@
+
+create_project -force -part $::env(XRAY_PART) design_fdre design_fdre
+read_verilog top_fdre.v
+
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports ce]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports sr]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports d]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_04) IOSTANDARD LVCMOS33" [get_ports q]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+set_property IS_ROUTE_FIXED 1 [get_nets -hierarchical]
+set_property IS_LOC_FIXED 1 [get_cells -hierarchical]
+set_property IS_BEL_FIXED 1 [get_cells -hierarchical]
+
+write_xdc -force fixed.xdc
+
+write_checkpoint -force design_fdre.dcp
+write_bitstream -force design_fdre.bit
+
+close_project
+
+foreach variant {fdse fdce fdpe} {
+	create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
+	read_verilog top_${variant}.v
+	read_xdc fixed.xdc
+
+	synth_design -top top
+	place_design
+	route_design
+
+	write_checkpoint -force design_${variant}.dcp
+	write_bitstream -force design_${variant}.bit
+
+	close_project
+}
+

minitests/fixedpnr/top_fdce.v

@@ -0,0 +1,12 @@
+
+module top(input clk, ce, sr, d, output q);
+	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
+	FDCE ff (
+		.C(clk),
+		.CE(ce),
+		.CLR(sr),
+		.D(d),
+		.Q(q)
+	);
+endmodule
+

minitests/fixedpnr/top_fdpe.v

@@ -0,0 +1,12 @@
+
+module top(input clk, ce, sr, d, output q);
+	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
+	FDPE ff (
+		.C(clk),
+		.CE(ce),
+		.PRE(sr),
+		.D(d),
+		.Q(q)
+	);
+endmodule
+

minitests/fixedpnr/top_fdre.v

@@ -0,0 +1,12 @@
+
+module top(input clk, ce, sr, d, output q);
+	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
+	FDRE ff (
+		.C(clk),
+		.CE(ce),
+		.R(sr),
+		.D(d),
+		.Q(q)
+	);
+endmodule
+

minitests/fixedpnr/top_fdse.v

@@ -0,0 +1,12 @@
+
+module top(input clk, ce, sr, d, output q);
+	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
+	FDSE ff (
+		.C(clk),
+		.CE(ce),
+		.S(sr),
+		.D(d),
+		.Q(q)
+	);
+endmodule
+