mirror of https://github.com/openXC7/prjxray.git
ffsrcemux fuzzer
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
8f770b3e6e
commit
5f5a9f7905
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@ -0,0 +1,9 @@
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/specimen_*
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/*.segbits
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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../../build/tools/segmatch -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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bash ../../utils/mergedb.sh clbll_l seg_clblx.segbits
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bash ../../utils/mergedb.sh clbll_r seg_clblx.segbits
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bash ../../utils/mergedb.sh clblm_l seg_clblx.segbits
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bash ../../utils/mergedb.sh clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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Purpose:
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Document CEUSEDMUX, SRUSEDMUX muxes
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Algorithm:
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Results:
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CEUSEDMUX: whether clock enable (CE) is used or clock always on
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0: always on
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1: controlled
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CLB.SLICE_X0.CEUSEDMUX 00_39
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CLB.SLICE_X1.CEUSEDMUX <0 candidates>
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SRUSEDMUX: whether FF can be reset or simply uses D value
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(How used when SR?)
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0: never reset
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1: controlled
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CLB.SLICE_X0.SRUSEDMUX 00_35
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CLB.SLICE_X1.SRUSEDMUX <0 candidates>
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#!/usr/bin/env python3
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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print("Loading tags")
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'''
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name,loc,ce,r
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clb_FDRE,SLICE_X12Y100,1,0
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clb_FDRE,SLICE_X13Y100,1,1
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clb_FDRE,SLICE_X14Y100,1,1
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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name,site,ce,r = l.split(',')
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ce = int(ce)
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r = int(r)
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# Theory: default position are the force positions
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# parameter FORCE_CE1=0;
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# parameter nFORCE_R0=1;
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# .CE(din[0] | FORCE_CE1),
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# .R(din[1] & nFORCE_R0),
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segmk.addtag(site, "CEUSEDMUX", ce ^ 1)
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segmk.addtag(site, "SRUSEDMUX", r)
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segmk.compile()
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segmk.write()
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#!/bin/bash
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set -ex
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. ../../utils/genheader.sh
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# Get all FF's in pblock
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set ffs [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ *} */*FF]
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set fp [open "design.txt" w]
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# set ff [lindex $ffs 0]
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# set ff [get_bels SLICE_X23Y100/AFF]
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# proc putl {lst} { foreach line $lst {puts $line} }
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foreach ff $ffs {
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set tile [get_tile -of_objects $ff]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set type [get_property TYPE $tile]
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set bel_type [get_property TYPE $ff]
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set used [get_property IS_USED $ff]
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set usedstr ""
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if $used {
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set ffc [get_cells -of_objects $ff]
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set cell_bel [get_property BEL $ffc]
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# ex: FDRE
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set ref_name [get_property REF_NAME $ffc]
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#set cinv [get_property IS_C_INVERTED $ffc]
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set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C}]
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set cinv [get_property IS_INVERTED $cpin]
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set usedstr "$cell_bel $ref_name $cinv"
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}
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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}
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close $fp
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@ -0,0 +1,109 @@
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import random
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random.seed(0)
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CLBN = 600
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# SLICE_X12Y100
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# SLICE_X27Y149
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SLICEX = (12, 28)
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SLICEY = (100, 150)
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 4
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DOUT_N = CLBN * 1
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ffprims = (
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'FDRE',
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)
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ff_bels = (
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'AFF',
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'A5FF',
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'BFF',
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'B5FF',
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'CFF',
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'C5FF',
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'DFF',
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'D5FF',
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)
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('name,loc,ce,r\n')
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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ffprim = random.choice(ffprims)
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force_ce = random.randint(0, 1)
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force_r = random.randint(0, 1)
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# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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loc = next(slices)
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#bel = random.choice(ff_bels)
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bel = "AFF"
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name = 'clb_%s' % ffprim
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print(' %s' % name)
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print(' #(.LOC("%s"), .BEL("%s"), .FORCE_CE1(%d), .nFORCE_R0(%d))' % (loc, bel, force_ce, force_r))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i))
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f.write('%s,%s,%s,%s\n' % (name, loc, force_ce, force_r))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module clb_FDRE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y114";
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parameter BEL="AFF";
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parameter FORCE_CE1=0;
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parameter nFORCE_R0=1;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDRE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0] | FORCE_CE1),
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.R(din[1] & nFORCE_R0),
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.D(din[2])
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);
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endmodule
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''')
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