From 89147532116380072857124683133c4228486e9a Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Thu, 24 Oct 2019 17:45:04 +0200
Subject: [PATCH] run make format

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 fuzzers/036-iob-ologic/generate.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/fuzzers/036-iob-ologic/generate.py b/fuzzers/036-iob-ologic/generate.py
index 3c706ac9..f8f56ec9 100644
--- a/fuzzers/036-iob-ologic/generate.py
+++ b/fuzzers/036-iob-ologic/generate.py
@@ -23,8 +23,7 @@ def handle_data_width(segmk, d):
 
     for opt in [2, 3, 4, 5, 6, 7, 8]:
         segmk.add_site_tag(
-            site, 'OSERDES.DATA_WIDTH.W{}'.format(opt),
-            d['DATA_WIDTH'] == opt)
+            site, 'OSERDES.DATA_WIDTH.W{}'.format(opt), d['DATA_WIDTH'] == opt)
 
     if verilog.unquote(d['DATA_RATE_OQ']) == 'DDR':
         # DDR + WIDTH 6/8 have some overlapping bits, create a feature.