mirror of https://github.com/openXC7/prjxray.git
063-gtp-common-conf: fix naming of GTREFCLK features
- Also adds a README for the fuzzer Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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@ -0,0 +1,33 @@
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GTPE2\_COMMON Primitive Configuration fuzzer
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============================================
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This fuzzer is used to document the parameters corresponding to the GTPE2\_COMMON primitive.
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It uses pre-built JSON containing a dictionary of parameters, each one with four attributes:
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- Type: one of Binary, Integer, String, Boolean.
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- Values: all possible values that this parameter can assume. In case of `BIN` types, the values list contains only the maximum value reachable.
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- Digits: number of digits (or bits) required to use a parameter.
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- Encoding: This is present only for `INT` types of parameters. These reflect the actual encoding of the parameter value in the bit array.
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E.g.:
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```json
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{
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"PLL0_REFCLK_DIV": {
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"type": "INT",
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"values": [1, 2],
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"encoding": [16, 0],
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"digits": 5
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}
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}
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```
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In addition, there exist wires and PIPs that allow the connections of the `GTREFCLK` ports to clocks coming from the device fabric instead of the `IBUFDS_GTE2` primitive.
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In fact, if the clock comes from the device fabric, the physical `GTGREFCLK[01]` port is used instead of the `GTREFCLK[01]` one (even though the design's primitive port is always `GTREFCLK`).
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In the [User Guide (pg 27)](https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf), it is stated that the `GTGREFCLK[01]` port is used for "internal testing purposes".
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Using this port is highly discouraged to get the reference clock from the fabric, as the recommended way is to get the clock from an external source using the `IBUFDS_GTE2` primitive.
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Therefore, in addition to the parameters, `IN_USE` and `ZINV\INV` features, this fuzzer documents also the `GTREFCLK[01]_USED` and `BOTH_GTREFCLK[01]_USED` features.
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@ -91,7 +91,8 @@ def main():
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for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
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segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
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for param in ["GTREFCLK0", "GTREFCLK1", "BOTH_GTREFCLK_USED"]:
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for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
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"BOTH_GTREFCLK_USED"]:
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segmk.add_site_tag(site, param, params[param])
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for params in params_list:
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@ -165,7 +165,8 @@ IBUFDS_GTE2 #(
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verilog_ports = ""
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for param in ["GTREFCLK0", "GTREFCLK1", "BOTH_GTREFCLK_USED"]:
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for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
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"BOTH_GTREFCLK_USED"]:
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params[param] = 0
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if tile_name in ibufds_out_wires:
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@ -179,7 +180,7 @@ IBUFDS_GTE2 #(
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.GTREFCLK{}({}),""".format(location, wire)
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gtrefclk_ports_used += 1
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params["GTREFCLK{}".format(location)] = 1
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params["GTREFCLK{}_USED".format(location)] = 1
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if gtrefclk_ports_used == 2:
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params["BOTH_GTREFCLK_USED"] = 1
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