mirror of https://github.com/openXC7/prjxray.git
063-gtp-common-conf: get features corresponding to IBUFDS -> GTP
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
d9c9f18389
commit
cb9e308f7a
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@ -88,14 +88,11 @@ def main():
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segmk.add_site_tag(
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site, "%s[%u]" % (param, i), bitstr[i])
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for param, invert in [("GTGREFCLK1", 0), ("GTGREFCLK0", 0),
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("PLL0LOCKDETCLK", 1), ("PLL1LOCKDETCLK",
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1), ("DRPCLK", 1)]:
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if invert:
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segmk.add_site_tag(
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site, "ZINV_" + param, 1 ^ params[param])
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else:
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segmk.add_site_tag(site, "INV_" + param, params[param])
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for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
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segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
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for param in ["GTREFCLK0", "GTREFCLK1", "BOTH_GTREFCLK_USED"]:
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segmk.add_site_tag(site, param, params[param])
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for params in params_list:
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site = params["site"]
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@ -59,6 +59,56 @@ assign out = in;
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params_dict = {"tile_type": None}
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params_list = list()
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clkswing_cfg_tiles = dict()
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ibufds_out_wires = dict()
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for tile_name, _, site_name, site_type in gen_sites("IBUFDS_GTE2"):
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# Both the IBUFDS_GTE2 in the same tile need to have
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# the same CLKSWING_CFG parameter
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if tile_name not in clkswing_cfg_tiles:
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clkswing_cfg = random.randint(0, 3)
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clkswing_cfg_tiles[tile_name] = clkswing_cfg
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else:
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clkswing_cfg = clkswing_cfg_tiles[tile_name]
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in_use = bool(random.randint(0, 9))
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params = {
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"site":
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site_name,
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"tile":
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tile_name,
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"IN_USE":
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in_use,
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"CLKRCV_TRST":
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verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
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"CLKCM_CFG":
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verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
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"CLKSWING_CFG":
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clkswing_cfg,
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}
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if in_use:
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ibufds_out_wire = "{}_O".format(site_name)
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if tile_name not in ibufds_out_wires:
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ibufds_out_wires[tile_name] = list()
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ibufds_out_wires[tile_name].append(
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(ibufds_out_wire, int(site_name[-1]) % 2))
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print("wire {};".format(ibufds_out_wire))
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print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
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print(
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"""
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IBUFDS_GTE2 #(
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.CLKRCV_TRST({CLKRCV_TRST}),
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.CLKCM_CFG({CLKCM_CFG}),
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.CLKSWING_CFG({CLKSWING_CFG})
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) {site} (
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.O({out})
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);""".format(**params, out=ibufds_out_wire))
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params_list.append(params)
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for tile_name, tile_type, site_name, site_type in gen_sites(
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"GTPE2_COMMON"):
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@ -102,8 +152,7 @@ assign out = in;
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verilog_attr += """
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.{}({}),""".format(param, value_str)
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for param in ["GTGREFCLK1", "GTGREFCLK0", "PLL0LOCKDETCLK",
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"PLL1LOCKDETCLK", "DRPCLK"]:
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for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
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is_inverted = random.randint(0, 1)
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params[param] = is_inverted
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@ -114,51 +163,33 @@ assign out = in;
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verilog_attr = verilog_attr.rstrip(",")
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verilog_attr += "\n)"
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verilog_ports = ""
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for param in ["GTREFCLK0", "GTREFCLK1", "BOTH_GTREFCLK_USED"]:
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params[param] = 0
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if tile_name in ibufds_out_wires:
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gtrefclk_ports_used = 0
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for wire, location in ibufds_out_wires[tile_name]:
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if random.random() < 0.5:
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continue
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verilog_ports += """
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.GTREFCLK{}({}),""".format(location, wire)
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gtrefclk_ports_used += 1
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params["GTREFCLK{}".format(location)] = 1
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if gtrefclk_ports_used == 2:
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params["BOTH_GTREFCLK_USED"] = 1
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print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
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print(
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"""GTPE2_COMMON {attrs} {site} (
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.GTREFCLK0(1'b0),
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.GTREFCLK1(1'b0)
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);""".format(attrs=verilog_attr, site=site_name))
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params_list.append(params)
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clkswing_cfg_tiles = dict()
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for tile_name, _, site_name, site_type in gen_sites("IBUFDS_GTE2"):
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# Both the IBUFDS_GTE2 in the same tile need to have
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# the same CLKSWING_CFG parameter
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if tile_name not in clkswing_cfg_tiles:
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clkswing_cfg = random.randint(0, 3)
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clkswing_cfg_tiles[tile_name] = clkswing_cfg
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else:
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clkswing_cfg = clkswing_cfg_tiles[tile_name]
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in_use = bool(random.randint(0, 9))
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params = {
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"site":
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site_name,
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"tile":
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tile_name,
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"IN_USE":
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in_use,
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"CLKRCV_TRST":
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verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
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"CLKCM_CFG":
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verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
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"CLKSWING_CFG":
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clkswing_cfg,
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}
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if in_use:
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print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
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print(
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"""
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IBUFDS_GTE2 #(
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.CLKRCV_TRST({CLKRCV_TRST}),
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.CLKCM_CFG({CLKCM_CFG}),
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.CLKSWING_CFG({CLKSWING_CFG})
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) {site} (
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);""".format(**params))
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{ports}
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.DRPCLK(1'b0)
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);""".format(attrs=verilog_attr, ports=verilog_ports, site=site_name))
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params_list.append(params)
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