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Merge pull request #1657 from isi-rcg/add-dsp-ppips 

Fuzzer-071 Generates ppips for DSP
This commit is contained in:
Tim Ansell 2021-05-01 10:42:58 -07:00 committed by GitHub
parent ec5c38eab3 0a31c8c9d7
commit 83c6cd9101
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 25 additions and 0 deletions
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25
fuzzers/071-ppips/generate.tcl
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@ -90,6 +90,22 @@ proc write_bram_ppips_db {filename tile} {
close $fp
}
proc write_dsp_ppips_db {filename tile} {
set fp [open $filename "w"]
set tile [get_tiles $tile]
set tile_type [get_property TILE_TYPE $tile]
foreach pip [get_pips -of_objects $tile] {
set dst_wire [get_wires -downhill -of_objects $pip]
if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
set src_wire [get_wires -uphill -of_objects $pip]
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
}
}
close $fp
}
proc write_hclk_ppips_db {filename tile} {
set fp [open $filename "w"]
set tile [get_tiles $tile]
@ -281,6 +297,7 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
}
foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \
DSP_INT_INTERFACE_L DSP_INT_INTERFACE_R \
CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \
IO_INT_INTERFACE_R IO_INT_INTERFACE_L \
BRKH_INT HCLK_L HCLK_R HCLK_CMT \
@ -321,6 +338,14 @@ foreach tile_type {BRAM_L BRAM_R} {
}
}
foreach tile_type {DSP_L DSP_R} {
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
if {[llength $tiles] != 0} {
set tile [lindex $tiles 0]
write_dsp_ppips_db "ppips_[string tolower $tile_type].db" $tile
}
}
foreach tile_type {PSS0 PSS1 PSS2 PSS3 PSS4 INT_INTERFACE_PSS_L} {
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
if {[llength $tiles] != 0} {