mirror of https://github.com/openXC7/prjxray.git
make format
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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@ -291,10 +291,10 @@ def create_segment_for_int_lr(
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else:
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assert False, database[tile]["type"]
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if (
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database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
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database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_') or
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database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
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if (database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
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database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_')
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or
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database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
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# This INT_[LR] tile has no adjacent connectivity,
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# create a segment.
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add_segment(
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@ -16,6 +16,7 @@ def set_port_wires(ports, name, pin, wires_outside_roi):
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assert False, name
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def main():
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parser = argparse.ArgumentParser(
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description=
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@ -43,12 +44,12 @@ def main():
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grid = db.grid()
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roi = Roi(
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db=db,
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x1=j['info']['GRID_X_MIN'],
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y1=j['info']['GRID_Y_MIN'],
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x2=j['info']['GRID_X_MAX'],
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y2=j['info']['GRID_Y_MAX'],
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)
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db=db,
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x1=j['info']['GRID_X_MIN'],
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y1=j['info']['GRID_Y_MIN'],
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x2=j['info']['GRID_X_MAX'],
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y2=j['info']['GRID_Y_MAX'],
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)
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with open(args.pad_wires) as f:
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for l in f:
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