diff --git a/fuzzers/005-tilegrid/generate.py b/fuzzers/005-tilegrid/generate.py
index 1ed71d40..bfddd12e 100644
--- a/fuzzers/005-tilegrid/generate.py
+++ b/fuzzers/005-tilegrid/generate.py
@@ -291,10 +291,10 @@ def create_segment_for_int_lr(
     else:
         assert False, database[tile]["type"]
 
-    if (
-       database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
-       database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_') or
-       database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
+    if (database[adjacent_tile]['type'].startswith('INT_INTERFACE_') or
+            database[adjacent_tile]['type'].startswith('PCIE_INT_INTERFACE_')
+            or
+            database[adjacent_tile]['type'].startswith('GTP_INT_INTERFACE')):
         # This INT_[LR] tile has no adjacent connectivity,
         # create a segment.
         add_segment(
diff --git a/minitests/roi_harness/create_design_json.py b/minitests/roi_harness/create_design_json.py
index 653f2d50..1d127f70 100644
--- a/minitests/roi_harness/create_design_json.py
+++ b/minitests/roi_harness/create_design_json.py
@@ -16,6 +16,7 @@ def set_port_wires(ports, name, pin, wires_outside_roi):
 
     assert False, name
 
+
 def main():
     parser = argparse.ArgumentParser(
         description=
@@ -43,12 +44,12 @@ def main():
     grid = db.grid()
 
     roi = Roi(
-            db=db,
-            x1=j['info']['GRID_X_MIN'],
-            y1=j['info']['GRID_Y_MIN'],
-            x2=j['info']['GRID_X_MAX'],
-            y2=j['info']['GRID_Y_MAX'],
-            )
+        db=db,
+        x1=j['info']['GRID_X_MIN'],
+        y1=j['info']['GRID_Y_MIN'],
+        x2=j['info']['GRID_X_MAX'],
+        y2=j['info']['GRID_Y_MAX'],
+    )
 
     with open(args.pad_wires) as f:
         for l in f: