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clbram: improve WEMUX.CE solving 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-12-10 18:29:54 -08:00
parent 59f0f3e761
commit 7a85840699
3 changed files with 6 additions and 5 deletions
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2
fuzzers/018-clbram/Makefile
View File

@ -1,4 +1,4 @@
N := 1 N := 2
SLICEL ?= N SLICEL ?= N
include ../clb.mk include ../clb.mk

7
fuzzers/018-clbram/generate.py
View File

@ -105,7 +105,7 @@ for l in f:
else: else:
assert (0) assert (0)
# All entries here requiare D # All entries here require D
assert (ram[3]) assert (ram[3])
if module == 'my_RAM32X1D': if module == 'my_RAM32X1D':
@ -123,9 +123,8 @@ for l in f:
for beli, bel in enumerate('ABCD'): for beli, bel in enumerate('ABCD'):
segmk.add_site_tag(loc, "%sLUT.RAM" % bel, ram[beli]) segmk.add_site_tag(loc, "%sLUT.RAM" % bel, ram[beli])
# FIXME: quick fix # FIXME: quick fix
if bel in "AD": segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli])
segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli]) segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
def bitfilter(frame_idx, bit_idx): def bitfilter(frame_idx, bit_idx):

2
fuzzers/018-clbram/top.py
View File

@ -58,6 +58,8 @@ for clbi in range(CLBN):
bel_opts = [ bel_opts = [
'SRL16E', 'SRL16E',
'SRLC32E', 'SRLC32E',
# Weight LUT6 more heavily to make WEMUX.CE solve quicker
'LUT6',
'LUT6', 'LUT6',
] ]