From 7a858406994fbb29df74ecabe81b5d0425f376ba Mon Sep 17 00:00:00 2001
From: John McMaster <johndmcmaster@gmail.com>
Date: Mon, 10 Dec 2018 18:29:54 -0800
Subject: [PATCH] clbram: improve WEMUX.CE solving

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
---
 fuzzers/018-clbram/Makefile    | 2 +-
 fuzzers/018-clbram/generate.py | 7 +++----
 fuzzers/018-clbram/top.py      | 2 ++
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/fuzzers/018-clbram/Makefile b/fuzzers/018-clbram/Makefile
index a28b0d4b..ea7a36f3 100644
--- a/fuzzers/018-clbram/Makefile
+++ b/fuzzers/018-clbram/Makefile
@@ -1,4 +1,4 @@
-N := 1
+N := 2
 SLICEL ?= N
 include ../clb.mk
 
diff --git a/fuzzers/018-clbram/generate.py b/fuzzers/018-clbram/generate.py
index 8ca4da9c..cd69c562 100644
--- a/fuzzers/018-clbram/generate.py
+++ b/fuzzers/018-clbram/generate.py
@@ -105,7 +105,7 @@ for l in f:
         else:
             assert (0)
 
-        # All entries here requiare D
+        # All entries here require D
         assert (ram[3])
 
         if module == 'my_RAM32X1D':
@@ -123,9 +123,8 @@ for l in f:
     for beli, bel in enumerate('ABCD'):
         segmk.add_site_tag(loc, "%sLUT.RAM" % bel, ram[beli])
         # FIXME: quick fix
-        if bel in "AD":
-            segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli])
-            segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
+        segmk.add_site_tag(loc, "%sLUT.SRL" % bel, srl[beli])
+        segmk.add_site_tag(loc, "%sLUT.SMALL" % bel, size[beli])
 
 
 def bitfilter(frame_idx, bit_idx):
diff --git a/fuzzers/018-clbram/top.py b/fuzzers/018-clbram/top.py
index b612a2c0..a7a02280 100644
--- a/fuzzers/018-clbram/top.py
+++ b/fuzzers/018-clbram/top.py
@@ -58,6 +58,8 @@ for clbi in range(CLBN):
         bel_opts = [
             'SRL16E',
             'SRLC32E',
+            # Weight LUT6 more heavily to make WEMUX.CE solve quicker
+            'LUT6',
             'LUT6',
         ]