Run make format.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/060-bram-cascades/generate.py

@@ -26,7 +26,12 @@ with open("design.txt", "r") as f:
         pdir = int(pdir)
 
         if tile not in tiledata:
-            tiledata[tile] = {"type": tile_type, "pips": set(), "srcs": set(), "dsts": set()}
+            tiledata[tile] = {
+                "type": tile_type,
+                "pips": set(),
+                "srcs": set(),
+                "dsts": set()
+            }
 
         if tile_type not in pipdata:
             pipdata[tile_type] = {}

fuzzers/060-bram-cascades/top.py

@@ -6,6 +6,7 @@ from prjxray import util
 from prjxray.db import Database
 random.seed(int(os.getenv("SEED"), 16))
 
+
 def bram_count():
     db = Database(util.get_db_root())
     grid = db.grid()
@@ -21,6 +22,7 @@ def bram_count():
 
     return count
 
+
 class LutMaker(object):
     def __init__(self):
         self.input_lut_idx = 0
@@ -67,6 +69,7 @@ class LutMaker(object):
             );
             """.format(lut=lut)
 
+
 def sdp_bram(name, width, address_bits):
     depth = 2**address_bits
 
@@ -99,40 +102,42 @@ module {name}(
 
 endmodule
     '''.format(
-            name=name,
-            width=width,
-            address_bits=address_bits,
-            depth=depth,
-            )
+        name=name,
+        width=width,
+        address_bits=address_bits,
+        depth=depth,
+    )
+
 
 MAX_BRAM = 8
 
+
 def emit_sdp_bram(luts, name, modules, lines, width, address_bits):
     modules.append(sdp_bram(name=name, width=width, address_bits=address_bits))
 
-    lines.append('''
+    lines.append(
+        '''
     wire [{address_bits}-1:0] {name}_wraddr;
     wire [{address_bits}-1:0] {name}_rdaddr;
     '''.format(
-        name=name,
-        address_bits=address_bits,
+            name=name,
+            address_bits=address_bits,
         ))
 
     for bit in range(address_bits):
-        lines.append("""
+        lines.append(
+            """
     assign {name}_wraddr[{bit}] = {net};""".format(
-        name=name,
-        bit=bit,
-        net=luts.get_next_output_net()))
+                name=name, bit=bit, net=luts.get_next_output_net()))
 
     for bit in range(address_bits):
-        lines.append("""
+        lines.append(
+            """
     assign {name}_rdaddr[{bit}] = {net};""".format(
-        name=name,
-        bit=bit,
-        net=luts.get_next_output_net()))
+                name=name, bit=bit, net=luts.get_next_output_net()))
 
-    lines.append('''
+    lines.append(
+        '''
     (* KEEP, DONT_TOUCH *)
     {name} {name}_inst(
         .wraddr({name}_wraddr),
@@ -140,10 +145,13 @@ def emit_sdp_bram(luts, name, modules, lines, width, address_bits):
     );
     '''.format(name=name))
 
-    return width, address_bits, math.ceil(float(width)/72)*72*(2**address_bits)
+    return width, address_bits, math.ceil(
+        float(width) / 72) * 72 * (2**address_bits)
+
 
 def max_address_bits(width):
-    return math.floor(math.log(float(MAX_BRAM*36*1024)/width, 2))
+    return math.floor(math.log(float(MAX_BRAM * 36 * 1024) / width, 2))
+
 
 def random_sdp_bram(luts, name, modules, lines):
     sdp_choices = set()
@@ -151,16 +159,16 @@ def random_sdp_bram(luts, name, modules, lines):
     for width in (1, 2, 4, 8, 16, 18, 32, 36):
         sdp_choices.add((width, (1, max_address_bits(width))))
 
-    for nbram in range(2, MAX_BRAM+1):
-        sdp_choices.add((nbram*32, (1, max_address_bits(nbram*32))))
-        sdp_choices.add((nbram*36, (1, max_address_bits(nbram*36))))
-        sdp_choices.add((nbram*16, (1, max_address_bits(nbram*16))))
-        sdp_choices.add((nbram*32, (1, max_address_bits(nbram*32))))
+    for nbram in range(2, MAX_BRAM + 1):
+        sdp_choices.add((nbram * 32, (1, max_address_bits(nbram * 32))))
+        sdp_choices.add((nbram * 36, (1, max_address_bits(nbram * 36))))
+        sdp_choices.add((nbram * 16, (1, max_address_bits(nbram * 16))))
+        sdp_choices.add((nbram * 32, (1, max_address_bits(nbram * 32))))
 
         # Bias some wide but shallow BRAMs to toggle the lower address bits
         # more.
         for address_bits in range(1, 4):
-            sdp_choices.add((nbram*16, (address_bits, address_bits)))
+            sdp_choices.add((nbram * 16, (address_bits, address_bits)))
 
     sdp_choices = sorted(sdp_choices)
 
@@ -180,9 +188,10 @@ def run():
 
     idx = 0
     while count > MAX_BRAM:
-        width, address_bits, bits = random_sdp_bram(luts, "ram{}".format(idx), modules, lines)
+        width, address_bits, bits = random_sdp_bram(
+            luts, "ram{}".format(idx), modules, lines)
 
-        brams = math.ceil(bits/float(36*1024))
+        brams = math.ceil(bits / float(36 * 1024))
 
         count -= brams
 
@@ -195,8 +204,7 @@ def run():
     for module in modules:
         print(module)
 
-    print(
-        '''
+    print('''
 module top();
 ''')
 
@@ -211,4 +219,3 @@ module top();
 
 if __name__ == '__main__':
     run()
-

fuzzers/071-ppips/generate.tcl

@@ -72,7 +72,7 @@ proc write_bram_ppips_db {filename tile} {
             puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
         }
 
-        # LOGIC_OUTS pips appear to be always, even thought multiple inputs to 
+        # LOGIC_OUTS pips appear to be always, even thought multiple inputs to
         # the pip junction.  Best guess is that the underlying hardware is
         # actually just one wire, and there is no actually junction.
         if [string match "*LOGIC_OUTS*" dst_wire] {

utils/dbfixup.py

@@ -104,8 +104,7 @@ def zero_groups(tag, bits, zero_db, strict=True, verbose=False):
                     len(a), len(bits), bits_str(bits))
 
 
-def add_zero_bits(
-        fn_in, zero_db, clb_int=False, strict=True, verbose=False):
+def add_zero_bits(fn_in, zero_db, clb_int=False, strict=True, verbose=False):
     '''
     Add multibit entries
     This requires adding some zero bits (ex: !31_09)
@@ -160,7 +159,6 @@ def add_zero_bits(
                     drops += 1
                     continue
 
-
                 new_line = " ".join([tag] + sorted(bits))
 
             if re.match(r'.*<.*>.*', new_line):
@@ -227,6 +225,7 @@ def load_zero_db(fn):
         ret.append(l)
     return ret
 
+
 def remove_ambiguous_solutions(fn_in, db_lines, strict=True, verbose=True):
     """ Removes features with identical solutions.
 
@@ -245,13 +244,12 @@ def remove_ambiguous_solutions(fn_in, db_lines, strict=True, verbose=True):
         if bits in solutions:
             if strict:
                 assert False, "Found solution {} at least twice, in {} and {}".format(
-                        bits, feature, solutions[bits])
+                    bits, feature, solutions[bits])
             else:
                 dropped_solutions.add(bits)
         else:
             solutions[bits] = feature
 
-
     if strict:
         return 0, db_lines
 
@@ -277,8 +275,6 @@ def remove_ambiguous_solutions(fn_in, db_lines, strict=True, verbose=True):
     return drops, output_lines
 
 
-
-
 def update_seg_fns(
         fn_inouts, zero_db, clb_int, lazy=False, strict=True, verbose=False):
     seg_files = 0
@@ -289,22 +285,17 @@ def update_seg_fns(
             continue
 
         changes, new_lines = add_zero_bits(
-            fn_in,
-            zero_db,
-            clb_int=clb_int,
-            strict=strict,
-            verbose=verbose)
+            fn_in, zero_db, clb_int=clb_int, strict=strict, verbose=verbose)
 
         new_changes, final_lines = remove_ambiguous_solutions(
-                fn_in,
-                new_lines,
-                strict=strict,
-                verbose=verbose,
-                )
+            fn_in,
+            new_lines,
+            strict=strict,
+            verbose=verbose,
+        )
 
         changes += new_changes
 
-
         with open(fn_out, "w") as f:
             for line in sorted(final_lines):
                 print(line, file=f)
@@ -317,7 +308,6 @@ def update_seg_fns(
         (seg_files, seg_lines))
 
 
-
 def update_masks(db_root):
     for mask_db, src_dbs in [
         ("clbll_l", ("clbll_l", "int_l")),