mirror of https://github.com/openXC7/prjxray.git
102-bram-data: cleanup
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
parent
308fcb5749
commit
136221fa6f
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@ -2,7 +2,6 @@
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import sys, re, os
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sys.path.append("../../../utils/")
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from prjxray.segmaker import Segmaker
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c2i = {'0': 0, '1': 1}
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@ -1,19 +1,4 @@
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'''
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Need coverage for the following:
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RAM32X1S_N
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RAM32X1D
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RAM32M
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RAM64X1S_N
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RAM64X1D_N
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RAM64M
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RAM128X1S_N
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RAM128X1D
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RAM256X1S
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SRL16E_N
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SRLC32E_N
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Note: LUT6 was added to try to simplify reduction, although it might not be needed
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'''
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#!/usr/bin/env python
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import os
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import random
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@ -23,13 +8,6 @@ from prjxray import verilog
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import sys
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def gen_bram18():
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# yield "RAMB18_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMB18E1']):
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yield site_name
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def gen_bram36():
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#yield "RAMB36_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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@ -54,11 +32,8 @@ def randbits(n):
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return ''.join([random.choice(('0', '1')) for _x in range(n)])
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loci = 0
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def make(module, gen_locs, pdatan, datan):
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global loci
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loci = 0
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for loci, loc in enumerate(gen_locs()):
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if loci >= DUTN:
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@ -87,7 +62,6 @@ def make(module, gen_locs, pdatan, datan):
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assert loci == DUTN
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#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
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make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
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f.close()
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@ -98,74 +72,8 @@ print(
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''')
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# RAMB18E1
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print(
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'''
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module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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for i in range(8):
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print(
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" parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print('')
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for i in range(0x40):
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print(
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" parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print('')
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print('''\
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(* LOC=LOC *)
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RAMB18E1 #(''')
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for i in range(8):
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print(' .INITP_%02X(INITP_%02X),' % (i, i))
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print('')
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for i in range(0x40):
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print(' .INIT_%02X(INIT_%02X),' % (i, i))
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print('')
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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print(
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'''
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module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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