mirror of https://github.com/openXC7/prjxray.git
clb_ndi1mux minitest: prepare for fuzzer
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
30b1930d65
commit
671b9da2eb
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@ -4,9 +4,11 @@ Can either be an external signal, another LUT's data input, or another LUT's car
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Note: mux input pattern is irregular
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Result:
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Neither external input nor carry input set any unknown bits
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Unclear what is going on
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Maybe an earlier test incorrectly set these?
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Additionally, I could not get BDI1 to activate
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Maybe should do a closer pass on BI/DI, which may be easier to trigger
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The following bits are set for NI but not NMC31:
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bit 00_00 ADI1MUX.AI
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bit 00_20 BDI1MUX.BI
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bit 01_43 BDI1MUX.CI
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Additionally, test with unknown DI mux bits don't appear near NI bits
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There is something strange going on
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@ -41,38 +41,163 @@ module top(input clk, stb, di, output do);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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`define ALL1
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`ifdef ALL1
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//`define G1
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`ifdef G1
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//ok
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my_NDI1MUX_NMC31 #(.LOC("SLICE_X8Y100"))
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my_NDI1MUX_NMC31 #(.LOC("SLICE_X12Y100"))
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my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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/*
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//Can't find a valid solution
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my_NDI1MUX_NDI1 #(.LOC("SLICE_X8Y101"))
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my_NDI1MUX_NDI1 #(.LOC("SLICE_X12Y101"))
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my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8]));
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*/
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my_NDI1MUX_NI #(.LOC("SLICE_X8Y102"))
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my_NDI1MUX_NI #(.LOC("SLICE_X12Y102"))
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my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
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`endif
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`define SINGLE1
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`ifdef SINGLE1
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//ok
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my_ADI1MUX_BMC31 #(.LOC("SLICE_X10Y100"))
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my_ADI1MUX_BMC31 #(.LOC("SLICE_X14Y100"))
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my_ADI1MUX_BMC31(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
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//ok
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my_ADI1MUX_AI #(.LOC("SLICE_X10Y101"))
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my_ADI1MUX_AI #(.LOC("SLICE_X14Y101"))
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my_ADI1MUX_AI(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
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/*
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//bad
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my_ADI1MUX_BDI1 #(.LOC("SLICE_X10Y102"))
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my_ADI1MUX_BDI1 #(.LOC("SLICE_X14Y102"))
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my_ADI1MUX_BDI1(.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16]));
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*/
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my_BDI1MUX_DI #(.LOC("SLICE_X10Y103"))
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my_BDI1MUX_DI #(.LOC("SLICE_X14Y103"))
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my_BDI1MUX_DI(.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16]));
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`endif
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`define G2
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`ifdef G2
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my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y100"), .C31(0), .B31(0), .A31(0))
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my0(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
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my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y101"), .C31(0), .B31(0), .A31(1))
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my1(.clk(clk), .din(din[ 136 +: 8]), .dout(dout[ 136 +: 8]));
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my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y102"), .C31(0), .B31(1), .A31(0))
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my2(.clk(clk), .din(din[ 144 +: 8]), .dout(dout[ 144 +: 8]));
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my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y103"), .C31(1), .B31(0), .A31(0))
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my3(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8]));
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my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y104"), .C31(1), .B31(1), .A31(1))
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my4(.clk(clk), .din(din[ 160 +: 8]), .dout(dout[ 160 +: 8]));
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//Sets rarely seen mux position
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my_RAM64X1D2 #(.LOC("SLICE_X14Y100"))
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c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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`endif
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endmodule
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//NI => 1
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module my_NDI1MUX_NI_NMC31 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "SLICE_X6Y100";
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parameter C31 = 0;
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parameter B31 = 0;
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parameter A31 = 0;
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wire [3:0] q31;
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wire [3:0] lutd;
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assign lutd[3] = din[7];
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assign lutd[2] = C31 ? q31[3] : din[7];
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assign lutd[1] = B31 ? q31[2] : din[7];
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assign lutd[0] = A31 ? q31[1] : din[7];
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(* LOC=LOC, BEL="D6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutd (
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.Q(dout[0]),
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.Q31(q31[3]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[3]));
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(* LOC=LOC, BEL="C6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutc (
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.Q(dout[1]),
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.Q31(q31[2]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[2]));
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[2]),
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.Q31(q31[1]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[1]));
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) luta (
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.Q(dout[3]),
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.Q31(q31[0]),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(lutd[0]));
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endmodule
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module my_RAM64X1D2 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1D #(
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.INIT(64'h0),
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.IS_WCLK_INVERTED(1'b0)
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) ramb (
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.DPO(dout[1]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]),
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.A0(din[3]),
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.A1(din[4]),
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.A2(din[5]),
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.A3(din[6]),
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.A4(din[7]),
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.A5(din[0]),
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.DPRA0(din[1]),
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.DPRA1(din[2]),
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.DPRA2(din[3]),
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.DPRA3(din[4]),
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.DPRA4(din[5]),
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.DPRA5(din[6]));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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RAM64X1D #(
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.INIT(64'h0),
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.IS_WCLK_INVERTED(1'b0)
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) rama (
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.DPO(dout[0]),
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.D(din[0]),
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.WCLK(clk),
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.WE(din[2]),
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.A0(din[3]),
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.A1(din[4]),
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.A2(din[5]),
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.A3(din[6]),
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.A4(din[7]),
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.A5(din[0]),
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.DPRA0(din[1]),
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.DPRA1(din[2]),
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.DPRA2(din[3]),
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.DPRA3(din[4]),
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.DPRA4(din[5]),
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.DPRA5(din[6]));
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endmodule
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/****************************************************************************
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Tries to set all three muxes at once
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@ -244,11 +369,24 @@ Individual mux tests
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module my_ADI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BEL="A6LUT";
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wire mc31c;
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(* LOC=LOC, BEL=BEL *)
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/*
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//Dummy entry to make more similar to my_ADI1MUX_BMC31
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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) lutb (
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.Q(dout[1]),
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.Q31(),
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.A(din[4:0]),
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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*/
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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@ -264,12 +402,10 @@ endmodule
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//ok
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module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter BELO="B6LUT";
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parameter BELI="A6LUT";
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wire mc31b;
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(* LOC=LOC, BEL=BELO *)
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(* LOC=LOC, BEL="B6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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@ -280,7 +416,7 @@ module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
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.CE(din[5]),
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.CLK(din[6]),
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.D(din[7]));
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(* LOC=LOC, BEL=BELI *)
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(* LOC=LOC, BEL="A6LUT" *)
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SRLC32E #(
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.INIT(32'h00000000),
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.IS_CLK_INVERTED(1'b0)
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