From 671b9da2ebac59748dab6e11c0a5f285be2510a7 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 18 Dec 2017 19:05:53 -0800 Subject: [PATCH] clb_ndi1mux minitest: prepare for fuzzer Signed-off-by: John McMaster Signed-off-by: Tim 'mithro' Ansell --- minitests/clb_ndi1mux/README.txt | 12 ++- minitests/clb_ndi1mux/top.v | 172 +++++++++++++++++++++++++++---- 2 files changed, 161 insertions(+), 23 deletions(-) diff --git a/minitests/clb_ndi1mux/README.txt b/minitests/clb_ndi1mux/README.txt index e3509649..4c138c42 100644 --- a/minitests/clb_ndi1mux/README.txt +++ b/minitests/clb_ndi1mux/README.txt @@ -4,9 +4,11 @@ Can either be an external signal, another LUT's data input, or another LUT's car Note: mux input pattern is irregular Result: -Neither external input nor carry input set any unknown bits -Unclear what is going on -Maybe an earlier test incorrectly set these? -Additionally, I could not get BDI1 to activate -Maybe should do a closer pass on BI/DI, which may be easier to trigger +The following bits are set for NI but not NMC31: +bit 00_00 ADI1MUX.AI +bit 00_20 BDI1MUX.BI +bit 01_43 BDI1MUX.CI + +Additionally, test with unknown DI mux bits don't appear near NI bits +There is something strange going on diff --git a/minitests/clb_ndi1mux/top.v b/minitests/clb_ndi1mux/top.v index de5c1238..6577e083 100644 --- a/minitests/clb_ndi1mux/top.v +++ b/minitests/clb_ndi1mux/top.v @@ -41,38 +41,163 @@ module top(input clk, stb, di, output do); endmodule module roi(input clk, input [255:0] din, output [255:0] dout); -`define ALL1 -`ifdef ALL1 +//`define G1 +`ifdef G1 //ok - my_NDI1MUX_NMC31 #(.LOC("SLICE_X8Y100")) + my_NDI1MUX_NMC31 #(.LOC("SLICE_X12Y100")) my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); /* //Can't find a valid solution - my_NDI1MUX_NDI1 #(.LOC("SLICE_X8Y101")) + my_NDI1MUX_NDI1 #(.LOC("SLICE_X12Y101")) my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8])); */ - my_NDI1MUX_NI #(.LOC("SLICE_X8Y102")) + my_NDI1MUX_NI #(.LOC("SLICE_X12Y102")) my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); -`endif -`define SINGLE1 -`ifdef SINGLE1 //ok - my_ADI1MUX_BMC31 #(.LOC("SLICE_X10Y100")) + my_ADI1MUX_BMC31 #(.LOC("SLICE_X14Y100")) my_ADI1MUX_BMC31(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); //ok - my_ADI1MUX_AI #(.LOC("SLICE_X10Y101")) + my_ADI1MUX_AI #(.LOC("SLICE_X14Y101")) my_ADI1MUX_AI(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); /* //bad - my_ADI1MUX_BDI1 #(.LOC("SLICE_X10Y102")) + my_ADI1MUX_BDI1 #(.LOC("SLICE_X14Y102")) my_ADI1MUX_BDI1(.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16])); */ - my_BDI1MUX_DI #(.LOC("SLICE_X10Y103")) + + my_BDI1MUX_DI #(.LOC("SLICE_X14Y103")) my_BDI1MUX_DI(.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16])); `endif + +`define G2 +`ifdef G2 + my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y100"), .C31(0), .B31(0), .A31(0)) + my0(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8])); + my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y101"), .C31(0), .B31(0), .A31(1)) + my1(.clk(clk), .din(din[ 136 +: 8]), .dout(dout[ 136 +: 8])); + my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y102"), .C31(0), .B31(1), .A31(0)) + my2(.clk(clk), .din(din[ 144 +: 8]), .dout(dout[ 144 +: 8])); + my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y103"), .C31(1), .B31(0), .A31(0)) + my3(.clk(clk), .din(din[ 152 +: 8]), .dout(dout[ 152 +: 8])); + my_NDI1MUX_NI_NMC31 #(.LOC("SLICE_X12Y104"), .C31(1), .B31(1), .A31(1)) + my4(.clk(clk), .din(din[ 160 +: 8]), .dout(dout[ 160 +: 8])); + + //Sets rarely seen mux position + my_RAM64X1D2 #(.LOC("SLICE_X14Y100")) + c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +`endif + endmodule +//NI => 1 +module my_NDI1MUX_NI_NMC31 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + parameter C31 = 0; + parameter B31 = 0; + parameter A31 = 0; + + wire [3:0] q31; + + wire [3:0] lutd; + assign lutd[3] = din[7]; + assign lutd[2] = C31 ? q31[3] : din[7]; + assign lutd[1] = B31 ? q31[2] : din[7]; + assign lutd[0] = A31 ? q31[1] : din[7]; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(q31[3]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(lutd[3])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(q31[2]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(lutd[2])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(q31[1]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(lutd[1])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(q31[0]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(lutd[0])); +endmodule + +module my_RAM64X1D2 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + + (* LOC=LOC, KEEP, DONT_TOUCH *) + RAM64X1D #( + .INIT(64'h0), + .IS_WCLK_INVERTED(1'b0) + ) ramb ( + .DPO(dout[1]), + .D(din[0]), + .WCLK(clk), + .WE(din[2]), + .A0(din[3]), + .A1(din[4]), + .A2(din[5]), + .A3(din[6]), + .A4(din[7]), + .A5(din[0]), + .DPRA0(din[1]), + .DPRA1(din[2]), + .DPRA2(din[3]), + .DPRA3(din[4]), + .DPRA4(din[5]), + .DPRA5(din[6])); + + (* LOC=LOC, KEEP, DONT_TOUCH *) + RAM64X1D #( + .INIT(64'h0), + .IS_WCLK_INVERTED(1'b0) + ) rama ( + .DPO(dout[0]), + .D(din[0]), + .WCLK(clk), + .WE(din[2]), + .A0(din[3]), + .A1(din[4]), + .A2(din[5]), + .A3(din[6]), + .A4(din[7]), + .A5(din[0]), + .DPRA0(din[1]), + .DPRA1(din[2]), + .DPRA2(din[3]), + .DPRA3(din[4]), + .DPRA4(din[5]), + .DPRA5(din[6])); +endmodule /**************************************************************************** Tries to set all three muxes at once @@ -244,11 +369,24 @@ Individual mux tests module my_ADI1MUX_AI (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; - parameter BEL="A6LUT"; wire mc31c; - (* LOC=LOC, BEL=BEL *) + /* + //Dummy entry to make more similar to my_ADI1MUX_BMC31 + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[1]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + */ + (* LOC=LOC, BEL="A6LUT" *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0) @@ -264,12 +402,10 @@ endmodule //ok module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; - parameter BELO="B6LUT"; - parameter BELI="A6LUT"; wire mc31b; - (* LOC=LOC, BEL=BELO *) + (* LOC=LOC, BEL="B6LUT" *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0) @@ -280,7 +416,7 @@ module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout); .CE(din[5]), .CLK(din[6]), .D(din[7])); - (* LOC=LOC, BEL=BELI *) + (* LOC=LOC, BEL="A6LUT" *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)