From 6424e5a701a48e633f3d27194ee37710371231b6 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Sun, 27 Jan 2019 06:57:50 -0800 Subject: [PATCH] Add DSP INT fuzzer. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/005-tilegrid/Makefile | 5 + fuzzers/005-tilegrid/add_tdb.py | 1 + fuzzers/005-tilegrid/dsp_int/Makefile | 4 + fuzzers/005-tilegrid/dsp_int/generate.tcl | 21 +++ fuzzers/005-tilegrid/dsp_int/top.py | 160 ++++++++++++++++++++++ fuzzers/005-tilegrid/iob_int/Makefile | 2 +- 6 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 fuzzers/005-tilegrid/dsp_int/Makefile create mode 100644 fuzzers/005-tilegrid/dsp_int/generate.tcl create mode 100644 fuzzers/005-tilegrid/dsp_int/top.py diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile index 59575a36..6893174b 100644 --- a/fuzzers/005-tilegrid/Makefile +++ b/fuzzers/005-tilegrid/Makefile @@ -12,6 +12,7 @@ TILEGRID_TDB_DEPENDENCIES += bram_int/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += dsp/build/segbits_tilegrid.tdb +TILEGRID_TDB_DEPENDENCIES += dsp_int/build/segbits_tilegrid.tdb GENERATE_FULL_ARGS= ifeq (${XRAY_DATABASE}, zynq7) @@ -69,6 +70,9 @@ bram_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json dsp/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json cd dsp && $(MAKE) +dsp_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json + cd dsp_int && $(MAKE) + build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES) python3 add_tdb.py \ --fn-in build/basicdb/tilegrid.json \ @@ -97,6 +101,7 @@ clean: cd bram_block && $(MAKE) clean cd bram_int && $(MAKE) clean cd dsp && $(MAKE) clean + cd dsp_int && $(MAKE) clean cd monitor && $(MAKE) clean .PHONY: database pushdb clean run diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py index a16f7a63..37b38320 100644 --- a/fuzzers/005-tilegrid/add_tdb.py +++ b/fuzzers/005-tilegrid/add_tdb.py @@ -67,6 +67,7 @@ def run(fn_in, fn_out, verbose=False): ("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words), ("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words), ("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words), + ("dsp_int/build/segbits_tilegrid.tdb", int_frames, int_words), ] for (tdb_fn, frames, words) in tdb_fns: diff --git a/fuzzers/005-tilegrid/dsp_int/Makefile b/fuzzers/005-tilegrid/dsp_int/Makefile new file mode 100644 index 00000000..fc2d5350 --- /dev/null +++ b/fuzzers/005-tilegrid/dsp_int/Makefile @@ -0,0 +1,4 @@ +N ?= 10 +GENERATE_ARGS?="--oneval 0 --design params.csv --dword 1 --dframe 15" +include ../fuzzaddr/common.mk + diff --git a/fuzzers/005-tilegrid/dsp_int/generate.tcl b/fuzzers/005-tilegrid/dsp_int/generate.tcl new file mode 100644 index 00000000..cadfbf3e --- /dev/null +++ b/fuzzers/005-tilegrid/dsp_int/generate.tcl @@ -0,0 +1,21 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + set_property IS_ENABLED 0 [get_drc_checks {DSPS-3}] + set_property IS_ENABLED 0 [get_drc_checks {DSPS-5}] + + place_design + route_design + + write_checkpoint -force design.dcp + write_bitstream -force design.bit +} + +run diff --git a/fuzzers/005-tilegrid/dsp_int/top.py b/fuzzers/005-tilegrid/dsp_int/top.py new file mode 100644 index 00000000..fc9aa246 --- /dev/null +++ b/fuzzers/005-tilegrid/dsp_int/top.py @@ -0,0 +1,160 @@ +import os +import random +import itertools +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray.db import Database + + +def gen_dsps(): + db = Database(util.get_db_root()) + grid = db.grid() + for tile_name in sorted(grid.tiles()): + loc = grid.loc_of_tilename(tile_name) + gridinfo = grid.gridinfo_at_loc(loc) + + sites = [] + for site_name, site_type in gridinfo.sites.items(): + if site_type in ['DSP48E1']: + sites.append(site_name) + + sites.sort() + + if len(sites) == 0: + continue + + if gridinfo.tile_type[-1] == 'L': + int_grid_x = loc.grid_x + 2 + int_tile_type = 'INT_L' + else: + int_grid_x = loc.grid_x - 2 + int_tile_type = 'INT_R' + + int_tile_locs = [ + (int_grid_x, loc.grid_y), + (int_grid_x, loc.grid_y - 1), + (int_grid_x, loc.grid_y - 2), + (int_grid_x, loc.grid_y - 3), + (int_grid_x, loc.grid_y - 4), + ] + + int_tiles = [] + for int_tile_loc in int_tile_locs: + int_gridinfo = grid.gridinfo_at_loc(int_tile_loc) + assert int_gridinfo.tile_type == int_tile_type, ( + int_gridinfo.tile_type, int_tile_type) + + int_tiles.append(grid.tilename_at_loc(int_tile_loc)) + + yield tile_name, sites, int_tiles + + +def write_params(params): + pinstr = 'tile,val\n' + for tile, (val, ) in sorted(params.items()): + pinstr += '%s,%s\n' % (tile, val) + open('params.csv', 'w').write(pinstr) + + +def run(): + print(''' +module top(); + ''') + + params = {} + + sites = list(gen_dsps()) + fuzz_iter = iter(util.gen_fuzz_states(len(sites) * 5)) + for tile_name, dsp_sites, int_tiles in sites: + # Each DSP tile has 5 INT tiles. + # The following feature is used to toggle a one PIP in each INT tile + # + # For a DSP, there are the following INT tiles and the feature + # to toggle + # + # INT_L_X34Y89/INT_L.GFAN1->>IMUX_L30 :: D1.C36 = 0 + # INT_L_X34Y89/INT_L.GFAN1->>IMUX_L28 :: D1.CARRYINSEL1 = toggle + # + # INT_L_X34Y88/INT_L.GFAN1->>IMUX_L30 :: D0.CARRYINSEL0 = toggle + # + # INT_L_X34Y87/INT_L.GFAN1->>IMUX_L5 :: D1.A29 = 0 + # INT_L_X34Y87/INT_L.GFAN1->>IMUX_L14 :: D1.B8 = toggle + # + # INT_L_X34Y86/INT_L.GFAN1->>IMUX_L30 :: D1.B4 = 0 + # INT_L_X34Y86/INT_L.GFAN1->>IMUX_L28 :: D1.B6 = toggle + # + # INT_L_X34Y85/INT_L.GFAN1->>IMUX_L30 :: Dark Green :: D1.C20 = 0 + # INT_L_X34Y85/INT_L.GFAN1->>IMUX_L28 :: Color 10 :: D1.B2 = toggle + (d1_carryinsel1, d0_carryinsel0, d1_b8, d1_b6, d1_b2 + ) = itertools.islice(fuzz_iter, 5) + params[int_tiles[0]] = (d1_carryinsel1, ) + params[int_tiles[1]] = (d0_carryinsel0, ) + params[int_tiles[2]] = (d1_b8, ) + params[int_tiles[3]] = (d1_b6, ) + params[int_tiles[4]] = (d1_b2, ) + + print( + ''' + wire [6:0] {dsp_site0}_opmode; + wire [2:0] {dsp_site0}_carryinsel; + + wire [29:0] {dsp_site1}_a; + wire [17:0] {dsp_site1}_b; + wire [47:0] {dsp_site1}_c; + wire [6:0] {dsp_site1}_opmode; + wire [2:0] {dsp_site1}_carryinsel; + + // INT 0 + assign {dsp_site1}_c[36] = 0; + assign {dsp_site1}_carryinsel[1] = {d1_carryinsel1}; + + // INT 1 + assign {dsp_site0}_carryinsel[0] = {d0_carryinsel0}; + + // INT 2 + assign {dsp_site1}_a[29] = 0; + assign {dsp_site1}_b[8] = {d1_b8}; + + // INT 3 + assign {dsp_site1}_b[4] = 0; + assign {dsp_site1}_b[6] = {d1_b6}; + + // INT 4 + assign {dsp_site1}_c[20] = 0; + assign {dsp_site1}_b[2] = {d1_b2}; + + (* KEEP, DONT_TOUCH, LOC = "{dsp_site0}" *) + DSP48E1 #( + .OPMODEREG(0), + .CREG(0) + ) dsp_{dsp_site0} ( + .OPMODE({dsp_site0}_opmode), + .CARRYINSEL({dsp_site0}_carryinsel) + ); + + (* KEEP, DONT_TOUCH, LOC = "{dsp_site1}" *) + DSP48E1 #( + .OPMODEREG(0), + .CREG(0) + ) dsp_{dsp_site1} ( + .OPMODE({dsp_site1}_opmode), + .CARRYINSEL({dsp_site1}_carryinsel), + .A({dsp_site1}_a), + .B({dsp_site1}_b), + .C({dsp_site1}_c) + ); +'''.format( + dsp_site0=dsp_sites[0], + dsp_site1=dsp_sites[1], + d1_carryinsel1=d1_carryinsel1, + d0_carryinsel0=d0_carryinsel0, + d1_b8=d1_b8, + d1_b6=d1_b6, + d1_b2=d1_b2)) + + print("endmodule") + write_params(params) + + +if __name__ == '__main__': + run() diff --git a/fuzzers/005-tilegrid/iob_int/Makefile b/fuzzers/005-tilegrid/iob_int/Makefile index 885ee4c2..cd564940 100644 --- a/fuzzers/005-tilegrid/iob_int/Makefile +++ b/fuzzers/005-tilegrid/iob_int/Makefile @@ -1,3 +1,3 @@ N ?= 35 -GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 1" +GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 14 --dword 1" include ../fuzzaddr/common.mk