mirror of https://github.com/openXC7/prjxray.git
Remove unused class
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak
parent
b356ed2761
commit
630cebd0fb
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@ -4,7 +4,6 @@ add_library(libprjxray
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segbits_file_reader.cc
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xilinx/bitstream_writer.cc
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xilinx/configuration_packet.cc
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xilinx/configuration_packetizer.cc
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xilinx/configuration_register.cc
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xilinx/frames.cc
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xilinx/configuration.cc
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@ -52,7 +51,6 @@ if (PRJXRAY_BUILD_TESTING)
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xilinx/tests/xc7series/configuration_column_test.cc
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xilinx/tests/xc7series/configuration_test.cc
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xilinx/tests/xc7series/configuration_packet_test.cc
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xilinx/tests/xc7series/configuration_packetizer_test.cc
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xilinx/tests/xc7series/crc_test.cc
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xilinx/tests/xc7series/ecc_test.cc
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xilinx/tests/xc7series/frame_address_test.cc
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@ -1,72 +0,0 @@
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#ifndef PRJXRAY_LIB_XILINX_CONFIGURATION_PACKETIZER_H_
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#define PRJXRAY_LIB_XILINX_CONFIGURATION_PACKETIZER_H_
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#include <absl/types/optional.h>
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#include <absl/types/span.h>
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#include <prjxray/xilinx/configuration.h>
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namespace prjxray {
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namespace xilinx {
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template <typename ArchType>
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class ConfigurationPacketizer {
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public:
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class iterator
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: std::iterator<
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std::input_iterator_tag,
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ConfigurationPacket<typename ArchType::ConfRegType>> {
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public:
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iterator(
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const typename ArchType::Part* part,
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typename Configuration<ArchType>::FrameMap::const_iterator
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begin,
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typename Configuration<ArchType>::FrameMap::const_iterator
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end);
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iterator& operator++();
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bool operator==(const iterator& other) const;
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bool operator!=(const iterator& other) const;
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const ConfigurationPacket<typename ArchType::ConfRegType>&
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operator*() const;
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const ConfigurationPacket<typename ArchType::ConfRegType>*
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operator->() const;
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private:
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friend class ConfigurationPacketizer;
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enum class State {
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Start,
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FrameAddressWritten,
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FrameDataWritten,
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ZeroPadWritten,
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Finished,
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};
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const typename ArchType::Part* part_;
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State state_;
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typename Configuration<ArchType>::FrameMap::const_iterator
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frame_cur_;
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typename Configuration<ArchType>::FrameMap::const_iterator
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frame_end_;
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absl::optional<uint32_t> frame_address_;
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absl::optional<
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ConfigurationPacket<typename ArchType::ConfRegType>>
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packet_;
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int zero_pad_packets_to_write_;
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};
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ConfigurationPacketizer(const Configuration<ArchType>& config);
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iterator begin() const;
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iterator end() const;
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private:
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const Configuration<ArchType>& config_;
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};
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} // namespace xilinx
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} // namespace prjxray
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#endif // PRJXRAY_LIB_XILINX_CONFIGURATION_PACKETIZER_H_
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@ -1,162 +0,0 @@
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#include <absl/types/span.h>
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#include <prjxray/xilinx/configuration.h>
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#include <prjxray/xilinx/configuration_packetizer.h>
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namespace prjxray {
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namespace xilinx {
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template <typename ArchType>
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ConfigurationPacketizer<ArchType>::ConfigurationPacketizer(
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const Configuration<ArchType>& config)
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: config_(config) {}
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template <typename ArchType>
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typename ConfigurationPacketizer<ArchType>::iterator
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ConfigurationPacketizer<ArchType>::begin() const {
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return iterator(&config_.part(), config_.frames().begin(),
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config_.frames().end());
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}
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template <typename ArchType>
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typename ConfigurationPacketizer<ArchType>::iterator
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ConfigurationPacketizer<ArchType>::end() const {
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return iterator(&config_.part(), config_.frames().end(),
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config_.frames().end());
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}
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template <typename ArchType>
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ConfigurationPacketizer<ArchType>::iterator::iterator(
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const typename ArchType::Part* part,
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typename Configuration<ArchType>::FrameMap::const_iterator begin,
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typename Configuration<ArchType>::FrameMap::const_iterator end)
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: part_(part),
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state_(begin != end ? State::Start : State::Finished),
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frame_cur_(begin),
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frame_end_(end) {
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this->operator++();
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}
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template <typename ArchType>
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const ConfigurationPacket<typename ArchType::ConfRegType>&
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ConfigurationPacketizer<ArchType>::iterator::operator*() const {
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return *packet_;
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}
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template <typename ArchType>
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const ConfigurationPacket<typename ArchType::ConfRegType>*
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ConfigurationPacketizer<ArchType>::iterator::operator->() const {
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return &(*packet_);
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}
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template <typename ArchType>
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bool ConfigurationPacketizer<ArchType>::iterator::operator==(
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const ConfigurationPacketizer<ArchType>::iterator& other) const {
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return state_ == other.state_ && frame_cur_ == other.frame_cur_;
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}
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template <typename ArchType>
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bool ConfigurationPacketizer<ArchType>::iterator::operator!=(
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const ConfigurationPacketizer<ArchType>::iterator& other) const {
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return !(*this == other);
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}
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template <>
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typename ConfigurationPacketizer<Series7>::iterator&
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ConfigurationPacketizer<Series7>::iterator::operator++() {
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using ArchType = Series7;
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// Frames are accessed via an indirect addressing scheme using the FAR
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// and FDRI registers. Writes begin with writing the target frame
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// address to FAR and then the frame data is written to FDRI. The
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// following state machine primarily follows that flow:
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// Start -> FrameAddressWritten -> FrameDataWritten -> Start....
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// When the last frame within a row is written, 2 full frames (202
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// words) of zero padding need to be written after the frame data.
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switch (state_) {
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case State::FrameDataWritten: {
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// If this is the last address in this row (i.e. the
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// next valid address known by the part is in a
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// different row, half, or bus type), start a zero fill.
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// Otherwise, increment the frame iterator and fall
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// through to Start.
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auto& this_address = frame_cur_->first;
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auto next_address =
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part_->GetNextFrameAddress(frame_cur_->first);
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if (next_address &&
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(next_address->block_type() !=
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this_address.block_type() ||
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next_address->is_bottom_half_rows() !=
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this_address.is_bottom_half_rows() ||
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next_address->row() != this_address.row())) {
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zero_pad_packets_to_write_ = 202;
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// Type 0 frames aren't documented in UG470. In
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// practice, they are used to zero pad in the
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// bitstream.
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packet_ = ConfigurationPacket<
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typename ArchType::ConfRegType>(
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0,
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ConfigurationPacket<
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typename ArchType::ConfRegType>::
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Opcode::NOP,
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ArchType::ConfRegType::CRC, {});
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state_ = State::ZeroPadWritten;
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break;
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}
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++frame_cur_;
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}
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case State::Start:
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if (frame_cur_ == frame_end_) {
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state_ = State::Finished;
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frame_address_.reset();
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packet_.reset();
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return *this;
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}
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frame_address_ = frame_cur_->first;
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packet_ = ConfigurationPacket<
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typename ArchType::ConfRegType>(
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1,
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ConfigurationPacket<
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typename ArchType::ConfRegType>::Opcode::Write,
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ArchType::ConfRegType::FAR,
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absl::Span<uint32_t>(&frame_address_.value(), 1));
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state_ = State::FrameAddressWritten;
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break;
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case State::FrameAddressWritten:
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packet_ = ConfigurationPacket<
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typename ArchType::ConfRegType>(
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1,
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ConfigurationPacket<
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typename ArchType::ConfRegType>::Opcode::Write,
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ArchType::ConfRegType::FDRI, frame_cur_->second);
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state_ = State::FrameDataWritten;
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break;
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case State::ZeroPadWritten:
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if (--zero_pad_packets_to_write_ == 1) {
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++frame_cur_;
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state_ = State::Start;
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}
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break;
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case State::Finished:
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break;
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}
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return *this;
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}
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template ConfigurationPacketizer<Series7>::ConfigurationPacketizer(
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const Configuration<Series7>& config);
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template ConfigurationPacketizer<Series7>::iterator
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ConfigurationPacketizer<Series7>::begin() const;
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template ConfigurationPacketizer<Series7>::iterator
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ConfigurationPacketizer<Series7>::end() const;
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template const ConfigurationPacket<typename Series7::ConfRegType>&
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ConfigurationPacketizer<Series7>::iterator::operator*() const;
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template const ConfigurationPacket<typename Series7::ConfRegType>*
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ConfigurationPacketizer<Series7>::iterator::operator->() const;
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template bool ConfigurationPacketizer<Series7>::iterator::operator==(
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const ConfigurationPacketizer<Series7>::iterator& other) const;
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template bool ConfigurationPacketizer<Series7>::iterator::operator!=(
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const ConfigurationPacketizer<Series7>::iterator& other) const;
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} // namespace xilinx
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} // namespace prjxray
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@ -1,119 +0,0 @@
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#include <map>
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#include <vector>
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#include <gtest/gtest.h>
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#include <prjxray/xilinx/architectures.h>
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#include <prjxray/xilinx/configuration_packetizer.h>
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using namespace prjxray::xilinx;
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TEST(ConfigurationPacketizerTest, EmptyConfigGeneratesNoPackets) {
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auto part = xc7series::Part::FromFile("configuration_test.yaml");
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ASSERT_TRUE(part);
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std::map<xc7series::FrameAddress, std::vector<uint32_t>> frames;
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Configuration<Series7> config(*part, &frames);
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ConfigurationPacketizer<Series7> packetizer(config);
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EXPECT_EQ(packetizer.begin(), packetizer.end());
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}
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TEST(ConfigurationPacketizerTest, ConfigWithFramesGeneratesPackets) {
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auto part = xc7series::Part::FromFile("configuration_test.yaml");
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ASSERT_TRUE(part);
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std::map<xc7series::FrameAddress, std::vector<uint32_t>> frames;
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frames[0] = std::vector<uint32_t>(101, 0xAA);
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frames[1] = std::vector<uint32_t>(101, 0xBB);
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Configuration<Series7> config(*part, &frames);
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EXPECT_EQ(config.frames().at(0), frames[0]);
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EXPECT_EQ(config.frames().at(1), frames[1]);
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ConfigurationPacketizer<Series7> packetizer(config);
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auto packet = packetizer.begin();
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ASSERT_NE(packet, packetizer.end());
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// Write 0x0 to FAR
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(1));
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EXPECT_EQ(packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::Write);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::FAR);
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EXPECT_EQ(packet->data(), std::vector<uint32_t>{0});
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++packet;
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ASSERT_NE(packet, packetizer.end());
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(1));
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EXPECT_EQ(packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::Write);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::FDRI);
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EXPECT_EQ(packet->data(), frames[0]);
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++packet;
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ASSERT_NE(packet, packetizer.end());
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(1));
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EXPECT_EQ(packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::Write);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::FAR);
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EXPECT_EQ(packet->data(), std::vector<uint32_t>{1});
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++packet;
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ASSERT_NE(packet, packetizer.end());
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(1));
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EXPECT_EQ(packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::Write);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::FDRI);
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EXPECT_EQ(packet->data(), frames[1]);
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++packet;
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EXPECT_EQ(packet, packetizer.end());
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}
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TEST(ConfigurationPacketizerTest, ConfigWithFrameAtEndOfRowGeneratesZerofill) {
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auto part = xc7series::Part::FromFile("configuration_test.yaml");
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ASSERT_TRUE(part);
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xc7series::FrameAddress last_frame_in_first_row(
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xc7series::BlockType::CLB_IO_CLK, false, 0, 43, 41);
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std::map<xc7series::FrameAddress, std::vector<uint32_t>> frames;
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frames[last_frame_in_first_row] = std::vector<uint32_t>(101, 0xAA);
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Configuration<Series7> config(*part, &frames);
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ConfigurationPacketizer<Series7> packetizer(config);
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auto packet = packetizer.begin();
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ASSERT_NE(packet, packetizer.end());
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(1));
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EXPECT_EQ(packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::Write);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::FAR);
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EXPECT_EQ(packet->data(),
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std::vector<uint32_t>{last_frame_in_first_row});
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++packet;
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ASSERT_NE(packet, packetizer.end());
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(1));
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EXPECT_EQ(packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::Write);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::FDRI);
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EXPECT_EQ(packet->data(), frames[last_frame_in_first_row]);
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for (int ii = 0; ii < 202; ++ii) {
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++packet;
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ASSERT_NE(packet, packetizer.end());
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EXPECT_EQ(packet->header_type(), static_cast<unsigned int>(0));
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EXPECT_EQ(
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packet->opcode(),
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ConfigurationPacket<Series7::ConfRegType>::Opcode::NOP);
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EXPECT_EQ(packet->address(), Series7::ConfRegType::CRC);
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EXPECT_EQ(packet->data(), std::vector<uint32_t>());
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}
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++packet;
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EXPECT_EQ(packet, packetizer.end());
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}
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