diff --git a/fuzzers/014-ffsrcemux/.gitignore b/fuzzers/014-ffsrcemux/.gitignore new file mode 100644 index 00000000..bdbf9bd6 --- /dev/null +++ b/fuzzers/014-ffsrcemux/.gitignore @@ -0,0 +1,9 @@ +/.Xil +/design/ +/design.bit +/design.bits +/design.dcp +/usage_statistics_webtalk.* +/vivado* +/specimen_* +/*.segbits diff --git a/fuzzers/014-ffsrcemux/Makefile b/fuzzers/014-ffsrcemux/Makefile new file mode 100644 index 00000000..32b7915d --- /dev/null +++ b/fuzzers/014-ffsrcemux/Makefile @@ -0,0 +1,22 @@ +N := 1 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +database: $(SPECIMENS_OK) + ../../build/tools/segmatch -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS)) + +pushdb: + bash ../../utils/mergedb.sh clbll_l seg_clblx.segbits + bash ../../utils/mergedb.sh clbll_r seg_clblx.segbits + bash ../../utils/mergedb.sh clblm_l seg_clblx.segbits + bash ../../utils/mergedb.sh clblm_r seg_clblx.segbits + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v + +.PHONY: database pushdb clean + diff --git a/fuzzers/014-ffsrcemux/README.txt b/fuzzers/014-ffsrcemux/README.txt new file mode 100644 index 00000000..8ffd67e3 --- /dev/null +++ b/fuzzers/014-ffsrcemux/README.txt @@ -0,0 +1,21 @@ +Purpose: +Document CEUSEDMUX, SRUSEDMUX muxes + +Algorithm: + +Results: + +CEUSEDMUX: whether clock enable (CE) is used or clock always on +0: always on +1: controlled +CLB.SLICE_X0.CEUSEDMUX 00_39 +CLB.SLICE_X1.CEUSEDMUX <0 candidates> + + +SRUSEDMUX: whether FF can be reset or simply uses D value +(How used when SR?) +0: never reset +1: controlled +CLB.SLICE_X0.SRUSEDMUX 00_35 +CLB.SLICE_X1.SRUSEDMUX <0 candidates> + diff --git a/fuzzers/014-ffsrcemux/generate.py b/fuzzers/014-ffsrcemux/generate.py new file mode 100644 index 00000000..ce577863 --- /dev/null +++ b/fuzzers/014-ffsrcemux/generate.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 + +import sys, re + +sys.path.append("../../../utils/") +from segmaker import segmaker + +segmk = segmaker("design.bits") + +print("Loading tags") +''' +name,loc,ce,r +clb_FDRE,SLICE_X12Y100,1,0 +clb_FDRE,SLICE_X13Y100,1,1 +clb_FDRE,SLICE_X14Y100,1,1 +''' +f = open('params.csv', 'r') +f.readline() +for l in f: + name,site,ce,r = l.split(',') + ce = int(ce) + r = int(r) + + # Theory: default position are the force positions + # parameter FORCE_CE1=0; + # parameter nFORCE_R0=1; + # .CE(din[0] | FORCE_CE1), + # .R(din[1] & nFORCE_R0), + segmk.addtag(site, "CEUSEDMUX", ce ^ 1) + segmk.addtag(site, "SRUSEDMUX", r) +segmk.compile() +segmk.write() + diff --git a/fuzzers/014-ffsrcemux/generate.sh b/fuzzers/014-ffsrcemux/generate.sh new file mode 100644 index 00000000..d272452b --- /dev/null +++ b/fuzzers/014-ffsrcemux/generate.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +set -ex + +. ../../utils/genheader.sh + +#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh + +python3 ../top.py >top.v +vivado -mode batch -source ../generate.tcl + +for x in design*.bit; do + ../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x +done + +python3 ../generate.py + diff --git a/fuzzers/014-ffsrcemux/generate.tcl b/fuzzers/014-ffsrcemux/generate.tcl new file mode 100644 index 00000000..50983877 --- /dev/null +++ b/fuzzers/014-ffsrcemux/generate.tcl @@ -0,0 +1,58 @@ +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit + + + +# Get all FF's in pblock +set ffs [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ *} */*FF] + +set fp [open "design.txt" w] +# set ff [lindex $ffs 0] +# set ff [get_bels SLICE_X23Y100/AFF] +# proc putl {lst} { foreach line $lst {puts $line} } +foreach ff $ffs { + set tile [get_tile -of_objects $ff] + set grid_x [get_property GRID_POINT_X $tile] + set grid_y [get_property GRID_POINT_Y $tile] + set type [get_property TYPE $tile] + set bel_type [get_property TYPE $ff] + set used [get_property IS_USED $ff] + set usedstr "" + if $used { + set ffc [get_cells -of_objects $ff] + set cell_bel [get_property BEL $ffc] + # ex: FDRE + set ref_name [get_property REF_NAME $ffc] + #set cinv [get_property IS_C_INVERTED $ffc] + + set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C}] + set cinv [get_property IS_INVERTED $cpin] + set usedstr "$cell_bel $ref_name $cinv" + } + puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr" +} +close $fp + diff --git a/fuzzers/014-ffsrcemux/top.py b/fuzzers/014-ffsrcemux/top.py new file mode 100644 index 00000000..96a2c7f9 --- /dev/null +++ b/fuzzers/014-ffsrcemux/top.py @@ -0,0 +1,109 @@ +import random + +random.seed(0) + +CLBN = 600 +# SLICE_X12Y100 +# SLICE_X27Y149 +SLICEX = (12, 28) +SLICEY = (100, 150) +# 800 +SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0]) +print('//SLICEX: %s' % str(SLICEX)) +print('//SLICEY: %s' % str(SLICEY)) +print('//SLICEN: %s' % str(SLICEN)) +print('//Requested CLBs: %s' % str(CLBN)) + +def gen_slices(): + for slicey in range(*SLICEY): + for slicex in range(*SLICEX): + yield "SLICE_X%dY%d" % (slicex, slicey) + +DIN_N = CLBN * 4 +DOUT_N = CLBN * 1 +ffprims = ( + 'FDRE', +) +ff_bels = ( + 'AFF', + 'A5FF', + 'BFF', + 'B5FF', + 'CFF', + 'C5FF', + 'DFF', + 'D5FF', + ) + +print(''' +module top(input clk, stb, di, output do); + localparam integer DIN_N = %d; + localparam integer DOUT_N = %d; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule +''' % (DIN_N, DOUT_N)) + +f = open('params.csv', 'w') +f.write('name,loc,ce,r\n') +slices = gen_slices() +print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1)) +for i in range(CLBN): + ffprim = random.choice(ffprims) + force_ce = random.randint(0, 1) + force_r = random.randint(0, 1) + # clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0])); + # clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1])); + loc = next(slices) + #bel = random.choice(ff_bels) + bel = "AFF" + name = 'clb_%s' % ffprim + print(' %s' % name) + print(' #(.LOC("%s"), .BEL("%s"), .FORCE_CE1(%d), .nFORCE_R0(%d))' % (loc, bel, force_ce, force_r)) + print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i)) + f.write('%s,%s,%s,%s\n' % (name, loc, force_ce, force_r)) +f.close() +print('''endmodule + +// --------------------------------------------------------------------- + +''') + +print(''' +module clb_FDRE (input clk, input [3:0] din, output dout); + parameter LOC="SLICE_X16Y114"; + parameter BEL="AFF"; + parameter FORCE_CE1=0; + parameter nFORCE_R0=1; + (* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) + FDRE ff ( + .C(clk), + .Q(dout), + .CE(din[0] | FORCE_CE1), + .R(din[1] & nFORCE_R0), + .D(din[2]) + ); + endmodule +''') +