mirror of https://github.com/openXC7/prjxray.git
tools: Tool to generate part YAML from a debug bitstream
Signed-off-by: Rick Altherr <kc8apf@kc8apf.net> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
parent
195323e0c8
commit
5eb7e15ad3
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@ -9,3 +9,11 @@ target_link_libraries(bittool libprjxray gflags absl::strings absl::span)
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add_executable(frame_address_decoder frame_address_decoder.cc)
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target_link_libraries(frame_address_decoder libprjxray)
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add_executable(gen_part_base_yaml gen_part_base_yaml.cc)
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target_link_libraries(gen_part_base_yaml
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absl::optional
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absl::span
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libprjxray
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yaml-cpp
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)
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@ -0,0 +1,117 @@
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#include <libgen.h>
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#include <iomanip>
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#include <iostream>
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#include <sstream>
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#include <absl/types/optional.h>
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#include <absl/types/span.h>
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#include <prjxray/memory_mapped_file.h>
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#include <prjxray/xilinx/xc7series/bitstream_reader.h>
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#include <prjxray/xilinx/xc7series/configuration_frame_address.h>
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#include <yaml-cpp/yaml.h>
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namespace xc7series = prjxray::xilinx::xc7series;
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template<typename T>
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std::string HexString(T value) {
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std::ostringstream out;
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out << "0x" << std::hex << value;
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return out.str();
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}
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int main(int argc, char *argv[]) {
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if (argc < 2) {
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std::cerr << "ERROR: no input specified" << std::endl;
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std::cerr << "Usage: " << basename(argv[0])
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<< " <bit_file>"
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<< std::endl;
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return 1;
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}
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auto in_file_name = argv[1];
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auto in_file = prjxray::MemoryMappedFile::InitWithFile(in_file_name);
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if (!in_file) {
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std::cerr << "Unable to open bit file: " << in_file_name
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<< std::endl;
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return 1;
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}
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auto in_bytes = absl::Span<uint8_t>(
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static_cast<uint8_t*>(in_file->data()),
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in_file->size());
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auto reader = xc7series::BitstreamReader::InitWithBytes(in_bytes);
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if (!reader) {
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std::cerr << "Input doesn't look like a bitstream"
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<< std::endl;
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return 1;
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}
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bool found_fdri_write = false;
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std::vector<uint32_t> frame_addresses;
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absl::optional<uint32_t> idcode;
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for (auto packet : *reader) {
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if (packet.opcode() !=
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xc7series::ConfigurationPacket::Opcode::Write) {
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continue;
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}
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if (packet.address() ==
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xc7series::ConfigurationRegister::FDRI) {
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found_fdri_write = true;
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} else if ((packet.address() ==
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xc7series::ConfigurationRegister::IDCODE) &&
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packet.data().size() == 1) {
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idcode = packet.data()[0];
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} else if (found_fdri_write &&
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(packet.address() ==
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xc7series::ConfigurationRegister::LOUT) &&
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packet.data().size() == 1) {
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frame_addresses.push_back(packet.data()[0]);
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}
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}
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if (!idcode) {
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std::cerr << "No IDCODE found." << std::endl;
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return 1;
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}
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if (frame_addresses.empty()) {
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std::cerr << "No LOUT writes found. Was "
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<< "BITSTREAM.GENERAL.DEBUGBITSTREAM set to YES?"
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<< std::endl;
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return 1;
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}
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YAML::Node config_yaml;
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config_yaml.SetTag("xilinx/xc7series/part");
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config_yaml["idcode"] = HexString(*idcode);
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// So far, the addresses appear to be written in increasing order but
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// there is no guarantee. Sort them just in case.
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std::sort(frame_addresses.begin(), frame_addresses.end());
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YAML::Node regions = config_yaml["configuration_regions"];
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for (auto start_of_range = frame_addresses.begin();
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start_of_range != frame_addresses.end();
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) {
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auto end_of_range = start_of_range;
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while (end_of_range + 1 != frame_addresses.end() &&
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*(end_of_range + 1) == *end_of_range + 1) {
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++end_of_range;
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}
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YAML::Node region;
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region["start"] =
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xc7series::ConfigurationFrameAddress(*start_of_range);
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region["end"] =
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xc7series::ConfigurationFrameAddress(*end_of_range);
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regions.push_back(region);
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start_of_range = ++end_of_range;
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}
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std::cout << config_yaml << std::endl;
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return 0;
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}
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