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Add MMCM bool attributes 

Signed-off-by: Mitja Kleider <mitja@kleider.name>
This commit is contained in:
Mitja Kleider 2018-12-30 13:18:17 +01:00
parent a86fd6ed1a
commit 7f17e85307
4 changed files with 77 additions and 18 deletions
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16
fuzzers/031-mmcm/Makefile
View File

@ -3,20 +3,20 @@
N := 8
include ../fuzzer.mk
SEGDATAS=$(addsuffix /segdata_cmt_top_r_upper_t.txt,$(SPECIMENS))
SEGDATAS=$(addsuffix /segdata_cmt_top_r_lower_b.txt,$(SPECIMENS))
database: build/segbits_cmt_top_r_upper_t.db
database: build/segbits_cmt_top_r_lower_b.db
build/segbits_cmt_top_r_upper_t.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o build/segbits_cmt_top_r_upper_t.rdb $(SEGDATAS)
build/segbits_cmt_top_r_lower_b.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o build/segbits_cmt_top_r_lower_b.rdb $(SEGDATAS)
build/segbits_cmt_top_r_upper_t.db: build/segbits_cmt_top_r_upper_t.rdb
build/segbits_cmt_top_r_lower_b.db: build/segbits_cmt_top_r_lower_b.rdb
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
${XRAY_MASKMERGE} build/mask_cmt_top_r_upper_t.db $(SEGDATAS)
${XRAY_MASKMERGE} build/mask_cmt_top_r_lower_b.db $(SEGDATAS)
pushdb:
${XRAY_MERGEDB} cmt_top_r_upper_t build/segbits_cmt_top_r_upper_t.db
${XRAY_MERGEDB} mask_cmt_top_r_upper_t build/mask_cmt_top_r_upper_t.db
${XRAY_MERGEDB} cmt_top_r_lower_b build/segbits_cmt_top_r_lower_b.db
${XRAY_MERGEDB} mask_cmt_top_r_lower_b build/mask_cmt_top_r_lower_b.db
.PHONY: database pushdb

3
fuzzers/031-mmcm/README.md
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@ -0,0 +1,3 @@
# MMCM
`MMCME2_ADV` in [UG953](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug953-vivado-7series-libraries.pdf) lists the available attributes.

39
fuzzers/031-mmcm/generate.py
View File

@ -6,15 +6,39 @@ from prjxray.segmaker import Segmaker
from prjxray import verilog
def bus_tags(segmk, ps, site):
def clkout_tags(segmk, ps, site):
""" Notes:
First bit is only active for value 1, for 1-128 in total 14 bits are toggling.
The relation is not clear yet, multiplication of the value by 2 does not fully correlate.
"""
for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
# 1-128 => 0-127 for actual 7 bit value
paramadj = int(ps[param]) - 1
bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
paramadj = 2 * int(ps[param])
bitstr = [int(x) for x in "{0:08b}".format(paramadj)[::-1]]
# FIXME: only bits 0 and 1 resolving
# for i in range(7):
for i in range(2):
segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
for i in range(8):
# for i in range(2):
#if i in [0, 3, 5]:
# mybit = 1 ^ bitstr[i]
#else:
mybit = bitstr[i]
segmk.add_site_tag(site, '%s[%u]' % (param, i), mybit)
def misc_tags(segmk, ps, site):
for boolattr in [
'STARTUP_WAIT',
"CLKOUT4_CASCADE",
"CLKFBOUT_USE_FINE_PS",
"CLKOUT0_USE_FINE_PS",
"CLKOUT1_USE_FINE_PS",
"CLKOUT2_USE_FINE_PS",
"CLKOUT3_USE_FINE_PS",
#"CLKOUT4_USE_FINE_PS", # several bits are changing, needs investigation
"CLKOUT5_USE_FINE_PS",
"CLKOUT6_USE_FINE_PS"
]:
segmk.add_site_tag(site, boolattr, ps[boolattr] == '"TRUE"')
def run():
@ -30,7 +54,8 @@ def run():
assert j['module'] == 'my_MMCME2_ADV'
site = verilog.unquote(ps['LOC'])
bus_tags(segmk, ps, site)
#clkout_tags(segmk, ps, site)
misc_tags(segmk, ps, site)
segmk.compile()
segmk.write()

37
fuzzers/031-mmcm/top.py
View File

@ -10,7 +10,7 @@ import json
def gen_sites():
for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
["PLLE2_ADV"])):
["MMCME2_ADV"])):
yield site_name
@ -37,11 +37,22 @@ for loci, site in enumerate(sites):
params = {
"CLKOUT1_DIVIDE": random.randint(1, 128),
"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_CASCADE": random.choice(["\"TRUE\"", "\"FALSE\""]),
"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKFBOUT_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT0_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT1_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT2_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT3_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT4_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT5_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
"CLKOUT6_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
}
modname = "my_MMCME2_ADV"
verilog.instance(modname, "inst_%u" % loci, ports, params=params)
# LOC isn't support
# LOC isn't supported
params["LOC"] = verilog.quote(site)
j = {'module': modname, 'i': loci, 'params': params}
@ -67,6 +78,16 @@ module my_MMCME2_ADV (input clk, input [7:0] din, output [7:0] dout);
parameter CLKOUT6_DIVIDE = 1;
parameter DIVCLK_DIVIDE = 1;
parameter CLKFBOUT_MULT = 5;
parameter CLKOUT4_CASCADE = "FALSE";
parameter STARTUP_WAIT = "FALSE";
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
parameter CLKOUT0_USE_FINE_PS = "FALSE";
parameter CLKOUT1_USE_FINE_PS = "FALSE";
parameter CLKOUT2_USE_FINE_PS = "FALSE";
parameter CLKOUT3_USE_FINE_PS = "FALSE";
parameter CLKOUT4_USE_FINE_PS = "FALSE";
parameter CLKOUT5_USE_FINE_PS = "FALSE";
parameter CLKOUT6_USE_FINE_PS = "FALSE";
(* KEEP, DONT_TOUCH *)
MMCME2_ADV #(
@ -75,7 +96,17 @@ module my_MMCME2_ADV (input clk, input [7:0] din, output [7:0] dout);
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE)
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKFBOUT_USE_FINE_PS(CLKFBOUT_USE_FINE_PS),
.CLKOUT0_USE_FINE_PS(CLKOUT0_USE_FINE_PS),
.CLKOUT1_USE_FINE_PS(CLKOUT1_USE_FINE_PS),
.CLKOUT2_USE_FINE_PS(CLKOUT2_USE_FINE_PS),
.CLKOUT3_USE_FINE_PS(CLKOUT3_USE_FINE_PS),
.CLKOUT4_USE_FINE_PS(CLKOUT4_USE_FINE_PS),
.CLKOUT5_USE_FINE_PS(CLKOUT5_USE_FINE_PS),
.CLKOUT6_USE_FINE_PS(CLKOUT6_USE_FINE_PS)
) dut(
.CLKFBOUT(),
.CLKFBOUTB(),