mirror of https://github.com/openXC7/prjxray.git
Remove 070-tileconn, favoring 074-dump_all
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
8763438cff
commit
538344f192
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@ -1,3 +0,0 @@
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/specimen_*/
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/tileconn.json
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/run.ok
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@ -1,26 +0,0 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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cp specimen_001/tileconn.json tileconn.json
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pushdb:
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cp tileconn.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tileconn.json
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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run:
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$(MAKE) clean
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$(MAKE) database
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$(MAKE) pushdb
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touch run.ok
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ tileconn.json run.ok
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.PHONY: database pushdb run clean
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@ -1,117 +0,0 @@
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#!/usr/bin/env python3
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import os, sys, json, re
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tilenodes = dict()
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grid2tile = dict()
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database = dict()
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print("Loading %s grid." % os.getenv("XRAY_DATABASE"))
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with open("%s/%s/tilegrid.json" % (os.getenv("XRAY_DATABASE_DIR"),
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os.getenv("XRAY_DATABASE")), "r") as f:
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grid = json.load(f)
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for tile, tiledata in grid.items():
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grid_xy = (tiledata["grid_x"], tiledata["grid_y"])
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grid2tile[grid_xy] = tile
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print("Loading nodewires.txt.")
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with open("nodewires.txt") as f:
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for line in f:
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node, *wires = line.split()
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for wire in wires:
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wire_tile, wire_name = wire.split("/")
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if wire_tile not in tilenodes:
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tilenodes[wire_tile] = dict()
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tilenodes[wire_tile][node] = wire_name
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def filter_pair(type1, type2, wire1, wire2, delta_x, delta_y):
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if type1 in ["HCLK_L", "HCLK_R"]:
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is_vertical_wire = False
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if wire1.startswith("HCLK_S"): is_vertical_wire = True
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if wire1.startswith("HCLK_N"): is_vertical_wire = True
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if wire1.startswith("HCLK_W"): is_vertical_wire = True
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if wire1.startswith("HCLK_E"): is_vertical_wire = True
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if wire1.startswith("HCLK_LV"): is_vertical_wire = True
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if wire1.startswith("HCLK_BYP"): is_vertical_wire = True
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if wire1.startswith("HCLK_FAN"): is_vertical_wire = True
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if wire1.startswith("HCLK_LEAF_CLK_"): is_vertical_wire = True
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is_horizontal_wire = False
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if wire1.startswith("HCLK_CK_"): is_horizontal_wire = True
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if wire1.startswith("HCLK_INT_"): is_horizontal_wire = True
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assert is_vertical_wire != is_horizontal_wire
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if is_vertical_wire and delta_y == 0: return True
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if is_horizontal_wire and delta_x == 0: return True
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if type1 in ["INT_L", "INT_R"]:
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# the wires with underscore after BEG/END all connect vertically
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if (("BEG_" in wire1) or ("END_" in wire1)) and delta_y == 0:
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return True
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if type1 in ["BRKH_INT", "BRKH_B_TERM_INT", "T_TERM_INT"]:
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if delta_y == 0: return True
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return False
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def handle_pair(tile1, tile2):
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if tile1 not in tilenodes: return
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if tile2 not in tilenodes: return
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tile1data = grid[tile1]
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tile2data = grid[tile2]
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grid1_xy = (tile1data["grid_x"], tile1data["grid_y"])
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grid2_xy = (tile2data["grid_x"], tile2data["grid_y"])
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if grid1_xy > grid2_xy:
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return handle_pair(tile2, tile1)
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key = (
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tile1data["type"], tile2data["type"], grid2_xy[0] - grid1_xy[0],
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grid2_xy[1] - grid1_xy[1])
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wire_pairs = set()
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for node, wire1 in tilenodes[tile1].items():
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if node in tilenodes[tile2]:
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wire2 = tilenodes[tile2][node]
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if filter_pair(key[0], key[1], wire1, wire2, key[2], key[3]):
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continue
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if filter_pair(key[1], key[0], wire2, wire1, -key[2], -key[3]):
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continue
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wire_pairs.add((wire1, wire2))
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if key not in database:
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database[key] = wire_pairs
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else:
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database[key] &= wire_pairs
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for tile, tiledata in grid.items():
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grid_right_xy = (tiledata["grid_x"] + 1, tiledata["grid_y"])
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grid_below_xy = (tiledata["grid_x"], tiledata["grid_y"] + 1)
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if grid_right_xy in grid2tile:
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handle_pair(tile, grid2tile[grid_right_xy])
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if grid_below_xy in grid2tile:
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handle_pair(tile, grid2tile[grid_below_xy])
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print("Converting database.")
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json_db = list()
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for key in sorted(database.keys()):
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(t1, t2, dx, dy) = key
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entry = dict()
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entry["tile_types"] = [t1, t2]
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entry["grid_deltas"] = [dx, dy]
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entry["wire_pairs"] = list(sorted(database[key]))
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if len(entry["wire_pairs"]):
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json_db.append(entry)
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print("Writing tileconn.json.")
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with open("tileconn.json", "w") as f:
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print(json.dumps(json_db, sort_keys=True, indent="\t"), file=f)
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@ -1,8 +0,0 @@
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#!/bin/bash -x
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source ${XRAY_GENHEADER}
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vivado -mode batch -source ../generate.tcl
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python3 ../generate.py
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@ -1,29 +0,0 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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write_checkpoint -force design.dcp
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# write_bitstream -force design.bit
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source ../../../utils/utils.tcl
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set fp [open "nodewires.txt" w]
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foreach node [get_nodes -of_objects [roi_tiles]] {
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puts $fp "$node [get_wires -of_objects $node]"
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}
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close $fp
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@ -1,3 +0,0 @@
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module top(input a, output y);
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assign y = a;
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endmodule
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