From 538344f192bc126a82cdad5b221e9776ea86d951 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 15 Oct 2018 17:46:21 -0700 Subject: [PATCH] Remove 070-tileconn, favoring 074-dump_all Signed-off-by: John McMaster --- fuzzers/070-tileconn/.gitignore | 3 - fuzzers/070-tileconn/Makefile | 26 ------- fuzzers/070-tileconn/generate.py | 117 ------------------------------ fuzzers/070-tileconn/generate.sh | 8 -- fuzzers/070-tileconn/generate.tcl | 29 -------- fuzzers/070-tileconn/top.v | 3 - 6 files changed, 186 deletions(-) delete mode 100644 fuzzers/070-tileconn/.gitignore delete mode 100644 fuzzers/070-tileconn/Makefile delete mode 100644 fuzzers/070-tileconn/generate.py delete mode 100644 fuzzers/070-tileconn/generate.sh delete mode 100644 fuzzers/070-tileconn/generate.tcl delete mode 100644 fuzzers/070-tileconn/top.v diff --git a/fuzzers/070-tileconn/.gitignore b/fuzzers/070-tileconn/.gitignore deleted file mode 100644 index 6e99ca40..00000000 --- a/fuzzers/070-tileconn/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/specimen_*/ -/tileconn.json -/run.ok diff --git a/fuzzers/070-tileconn/Makefile b/fuzzers/070-tileconn/Makefile deleted file mode 100644 index 73b0a649..00000000 --- a/fuzzers/070-tileconn/Makefile +++ /dev/null @@ -1,26 +0,0 @@ - -N := 1 -SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) -SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) - -database: $(SPECIMENS_OK) - cp specimen_001/tileconn.json tileconn.json - -pushdb: - cp tileconn.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tileconn.json - -$(SPECIMENS_OK): - bash generate.sh $(subst /OK,,$@) - touch $@ - -run: - $(MAKE) clean - $(MAKE) database - $(MAKE) pushdb - touch run.ok - -clean: - rm -rf specimen_[0-9][0-9][0-9]/ tileconn.json run.ok - -.PHONY: database pushdb run clean - diff --git a/fuzzers/070-tileconn/generate.py b/fuzzers/070-tileconn/generate.py deleted file mode 100644 index 7a707ac8..00000000 --- a/fuzzers/070-tileconn/generate.py +++ /dev/null @@ -1,117 +0,0 @@ -#!/usr/bin/env python3 - -import os, sys, json, re - -tilenodes = dict() -grid2tile = dict() -database = dict() - -print("Loading %s grid." % os.getenv("XRAY_DATABASE")) -with open("%s/%s/tilegrid.json" % (os.getenv("XRAY_DATABASE_DIR"), - os.getenv("XRAY_DATABASE")), "r") as f: - grid = json.load(f) - -for tile, tiledata in grid.items(): - grid_xy = (tiledata["grid_x"], tiledata["grid_y"]) - grid2tile[grid_xy] = tile - -print("Loading nodewires.txt.") -with open("nodewires.txt") as f: - for line in f: - node, *wires = line.split() - for wire in wires: - wire_tile, wire_name = wire.split("/") - if wire_tile not in tilenodes: - tilenodes[wire_tile] = dict() - tilenodes[wire_tile][node] = wire_name - - -def filter_pair(type1, type2, wire1, wire2, delta_x, delta_y): - if type1 in ["HCLK_L", "HCLK_R"]: - is_vertical_wire = False - if wire1.startswith("HCLK_S"): is_vertical_wire = True - if wire1.startswith("HCLK_N"): is_vertical_wire = True - if wire1.startswith("HCLK_W"): is_vertical_wire = True - if wire1.startswith("HCLK_E"): is_vertical_wire = True - if wire1.startswith("HCLK_LV"): is_vertical_wire = True - if wire1.startswith("HCLK_BYP"): is_vertical_wire = True - if wire1.startswith("HCLK_FAN"): is_vertical_wire = True - if wire1.startswith("HCLK_LEAF_CLK_"): is_vertical_wire = True - - is_horizontal_wire = False - if wire1.startswith("HCLK_CK_"): is_horizontal_wire = True - if wire1.startswith("HCLK_INT_"): is_horizontal_wire = True - - assert is_vertical_wire != is_horizontal_wire - if is_vertical_wire and delta_y == 0: return True - if is_horizontal_wire and delta_x == 0: return True - - if type1 in ["INT_L", "INT_R"]: - # the wires with underscore after BEG/END all connect vertically - if (("BEG_" in wire1) or ("END_" in wire1)) and delta_y == 0: - return True - - if type1 in ["BRKH_INT", "BRKH_B_TERM_INT", "T_TERM_INT"]: - if delta_y == 0: return True - - return False - - -def handle_pair(tile1, tile2): - if tile1 not in tilenodes: return - if tile2 not in tilenodes: return - - tile1data = grid[tile1] - tile2data = grid[tile2] - - grid1_xy = (tile1data["grid_x"], tile1data["grid_y"]) - grid2_xy = (tile2data["grid_x"], tile2data["grid_y"]) - - if grid1_xy > grid2_xy: - return handle_pair(tile2, tile1) - - key = ( - tile1data["type"], tile2data["type"], grid2_xy[0] - grid1_xy[0], - grid2_xy[1] - grid1_xy[1]) - - wire_pairs = set() - - for node, wire1 in tilenodes[tile1].items(): - if node in tilenodes[tile2]: - wire2 = tilenodes[tile2][node] - if filter_pair(key[0], key[1], wire1, wire2, key[2], key[3]): - continue - if filter_pair(key[1], key[0], wire2, wire1, -key[2], -key[3]): - continue - wire_pairs.add((wire1, wire2)) - - if key not in database: - database[key] = wire_pairs - else: - database[key] &= wire_pairs - - -for tile, tiledata in grid.items(): - grid_right_xy = (tiledata["grid_x"] + 1, tiledata["grid_y"]) - grid_below_xy = (tiledata["grid_x"], tiledata["grid_y"] + 1) - - if grid_right_xy in grid2tile: - handle_pair(tile, grid2tile[grid_right_xy]) - - if grid_below_xy in grid2tile: - handle_pair(tile, grid2tile[grid_below_xy]) - -print("Converting database.") -json_db = list() -for key in sorted(database.keys()): - (t1, t2, dx, dy) = key - entry = dict() - entry["tile_types"] = [t1, t2] - entry["grid_deltas"] = [dx, dy] - entry["wire_pairs"] = list(sorted(database[key])) - if len(entry["wire_pairs"]): - json_db.append(entry) - -print("Writing tileconn.json.") -with open("tileconn.json", "w") as f: - print(json.dumps(json_db, sort_keys=True, indent="\t"), file=f) diff --git a/fuzzers/070-tileconn/generate.sh b/fuzzers/070-tileconn/generate.sh deleted file mode 100644 index f639d561..00000000 --- a/fuzzers/070-tileconn/generate.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/bash -x - -source ${XRAY_GENHEADER} - -vivado -mode batch -source ../generate.tcl - -python3 ../generate.py - diff --git a/fuzzers/070-tileconn/generate.tcl b/fuzzers/070-tileconn/generate.tcl deleted file mode 100644 index 71ea0321..00000000 --- a/fuzzers/070-tileconn/generate.tcl +++ /dev/null @@ -1,29 +0,0 @@ -create_project -force -part $::env(XRAY_PART) design design - -read_verilog ../top.v -synth_design -top top - -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y] - -create_pblock roi -resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" - -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] -set_param tcl.collectionResultDisplayLimit 0 - -place_design -route_design - -write_checkpoint -force design.dcp -# write_bitstream -force design.bit - -source ../../../utils/utils.tcl - -set fp [open "nodewires.txt" w] -foreach node [get_nodes -of_objects [roi_tiles]] { - puts $fp "$node [get_wires -of_objects $node]" -} -close $fp diff --git a/fuzzers/070-tileconn/top.v b/fuzzers/070-tileconn/top.v deleted file mode 100644 index 5a70fc18..00000000 --- a/fuzzers/070-tileconn/top.v +++ /dev/null @@ -1,3 +0,0 @@ -module top(input a, output y); - assign y = a; -endmodule