mirror of https://github.com/openXC7/prjxray.git
066-gtp-int-pips: add fuzzer for GTP_INT_INTERFACE DELAY PIPs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
53e1678dab
commit
5137498bcb
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@ -0,0 +1,55 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=gtp_int_interface
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SEG_TYPE?=gtp_int_interface
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PIPLIST_TCL=$(FUZDIR)/gtp_int_interface_pip_list.tcl
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BUILD_DIR = build
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RUN_OK = run.ok
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TODO_RE=".*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(SEG_TYPE) --re $(TODO_RE) --sides ""
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N = 2
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SEGMATCH_FLAGS=-c 1
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A_PIPLIST=gtp_int_interface.txt
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CHECK_ARGS= --zero-entries --timeout-iters 2
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include ../pip_loop.mk
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$(BUILD_DIR)/segbits_gtp_int_interface.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_gtp_int_interface.rdb \
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$(shell find $(BUILD_DIR) -name segdata_gtp_int_interface*.txt)
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RDBS = $(BUILD_DIR)/segbits_gtp_int_interface.rdb
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database: ${RDBS}
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${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
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--seg-fn-in $(BUILD_DIR)/segbits_gtp_int_interface.rdb \
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--seg-fn-out $(BUILD_DIR)/segbits_gtp_int_interface.db
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# Keep a copy to track iter progress
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cp $(BUILD_DIR)/segbits_gtp_int_interface.rdb $(BUILD_DIR)/$(ITER)/segbits_gtp_int_interface.rdb
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cp $(BUILD_DIR)/segbits_gtp_int_interface.db $(BUILD_DIR)/$(ITER)/segbits_gtp_int_interface.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db $(BUILD_DIR)/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} gtp_int_interface_l $(BUILD_DIR)/segbits_gtp_int_interface.db
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} gtp_int_interface_r $(BUILD_DIR)/segbits_gtp_int_interface.db
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} gtp_int_interface $(BUILD_DIR)/segbits_gtp_int_interface.db
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pushdb: database
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${XRAY_MERGEDB} gtp_int_interface_l $(BUILD_DIR)/segbits_gtp_int_interface.db
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${XRAY_MERGEDB} gtp_int_interface_r $(BUILD_DIR)/segbits_gtp_int_interface.db
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${XRAY_MERGEDB} gtp_int_interface $(BUILD_DIR)/segbits_gtp_int_interface.db
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.PHONY: database pushdb run clean
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@ -0,0 +1,99 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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word = int(word / 32)
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if frame not in [26, 27]:
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return False
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return True
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def read_pip_data(pipfile, pipdata, tile_ports):
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'gtp_int_interface', pipfile)) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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tile_ports = {}
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read_pip_data('gtp_int_interface.txt', pipdata, tile_ports)
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('GTP_INT_INTERFACE'):
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continue
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata["GTP_INT_INTERFACE"]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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else:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,67 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc route_delay {} {
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set nets [get_nets]
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foreach net $nets {
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set wire [get_wires -of_objects $net -filter { TILE_NAME =~ "*GTP_INT_INTERFACE*" && NAME =~ "*IMUX_OUT*" }]
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if { $wire == "" } {
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continue
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}
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if { rand() < 0.60 } {
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continue
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}
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set parts [split $wire "/"]
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set tile_name [lindex $parts 0]
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set wire_name [lindex $parts 1]
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set delay_wire_name [string map {OUT DELAY} $wire_name]
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set delay_node [get_nodes $tile_name/$delay_wire_name]
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if { $delay_node == "" } {
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exit 1
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}
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route_design -unroute -nets $net
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puts "Attempting to route net $net through $delay_node."
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route_via $net [list $delay_node]
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design -directive Quick
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route_design -directive Quick
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route_delay
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,47 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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proc print_tile_pips {tile_type filename} {
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set fp [open $filename w]
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set pips [dict create]
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foreach tile [get_tiles -filter "TYPE =~ $tile_type*"] {
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foreach pip [lsort [get_pips -of_objects $tile]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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# Skip pips with disconnected nodes
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set src_node [get_nodes -of_objects $src]
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if { $src_node == {} } {
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continue
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}
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set dst_node [get_nodes -of_objects $dst]
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if { $dst_node == {} } {
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continue
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}
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set src_wire [regsub {.*/} $src ""]
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set src_delay_match [regexp {DELAY} $src_wire]
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if { $src_delay_match } {
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set pip_string "GTP_INT_INTERFACE.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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if ![dict exists $pips $pip_string] {
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puts $fp $pip_string
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dict set pips $pip_string 1
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}
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}
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}
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}
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close $fp
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}
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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print_tile_pips GTP_INT_INTERFACE gtp_int_interface.txt
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@ -0,0 +1,196 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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ports = {
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"GTPE2_CHANNEL": [
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("CFGRESET", 1),
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("CLKRSVD0", 1),
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("CLKRSVD1", 1),
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("DMONFIFORESET", 1),
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("DMONITORCLK", 1),
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("DRPCLK", 1),
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("DRPEN", 1),
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("DRPWE", 1),
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("EYESCANMODE", 1),
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("EYESCANRESET", 1),
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("EYESCANTRIGGER", 1),
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("GTRESETSEL", 1),
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("GTRXRESET", 1),
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("GTTXRESET", 1),
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("PMARSVDIN0", 1),
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("PMARSVDIN1", 1),
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("PMARSVDIN2", 1),
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("PMARSVDIN3", 1),
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("PMARSVDIN4", 1),
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("RESETOVRD", 1),
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("RX8B10BEN", 1),
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("RXBUFRESET", 1),
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("RXCDRFREQRESET", 1),
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("RXCDRHOLD", 1),
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("RXCDROVRDEN", 1),
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("RXCDRRESET", 1),
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("RXCDRRESETRSV", 1),
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("RXCHBONDEN", 1),
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("RXCHBONDMASTER", 1),
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("RXCHBONDSLAVE", 1),
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("RXCOMMADETEN", 1),
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("RXDDIEN", 1),
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("RXDFEXYDEN", 1),
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("RXDLYBYPASS", 1),
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("RXDLYEN", 1),
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("RXDLYOVRDEN", 1),
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("RXDLYSRESET", 1),
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("RXGEARBOXSLIP", 1),
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("RXLPMHFHOLD", 1),
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("RXLPMHFOVRDEN", 1),
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("RXLPMLFHOLD", 1),
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("RXLPMLFOVRDEN", 1),
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("RXLPMOSINTNTRLEN", 1),
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("RXLPMRESET", 1),
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("RXMCOMMAALIGNEN", 1),
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("RXOOBRESET", 1),
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("RXOSCALRESET", 1),
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("RXOSHOLD", 1),
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("RXOSINTEN", 1),
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("RXOSINTHOLD", 1),
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("RXOSINTNTRLEN", 1),
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("RXOSINTOVRDEN", 1),
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("RXOSINTPD", 1),
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("RXOSINTSTROBE", 1),
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("RXOSINTTESTOVRDEN", 1),
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("RXOSOVRDEN", 1),
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("RXPCOMMAALIGNEN", 1),
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("RXPCSRESET", 1),
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("RXPHALIGN", 1),
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("RXPHALIGNEN", 1),
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("RXPHDLYPD", 1),
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("RXPHDLYRESET", 1),
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("RXPHOVRDEN", 1),
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("RXPMARESET", 1),
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("RXPOLARITY", 1),
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("RXPRBSCNTRESET", 1),
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("RXRATEMODE", 1),
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("RXSLIDE", 1),
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("RXSYNCALLIN", 1),
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("RXSYNCIN", 1),
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("RXSYNCMODE", 1),
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("RXUSERRDY", 1),
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("RXUSRCLK2", 1),
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("RXUSRCLK", 1),
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("SETERRSTATUS", 1),
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("SIGVALIDCLK", 1),
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("TX8B10BEN", 1),
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("TXCOMINIT", 1),
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("TXCOMSAS", 1),
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("TXCOMWAKE", 1),
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("TXDEEMPH", 1),
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("TXDETECTRX", 1),
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("TXDIFFPD", 1),
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("TXDLYBYPASS", 1),
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("TXDLYEN", 1),
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("TXDLYHOLD", 1),
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("TXDLYOVRDEN", 1),
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||||||
|
("TXDLYSRESET", 1),
|
||||||
|
("TXDLYUPDOWN", 1),
|
||||||
|
("TXELECIDLE", 1),
|
||||||
|
("TXINHIBIT", 1),
|
||||||
|
("TXPCSRESET", 1),
|
||||||
|
("TXPDELECIDLEMODE", 1),
|
||||||
|
("TXPHALIGN", 1),
|
||||||
|
("TXPHALIGNEN", 1),
|
||||||
|
("TXPHDLYPD", 1),
|
||||||
|
("TXPHDLYRESET", 1),
|
||||||
|
("TXPHDLYTSTCLK", 1),
|
||||||
|
("TXPHINIT", 1),
|
||||||
|
("TXPHOVRDEN", 1),
|
||||||
|
("TXPIPPMEN", 1),
|
||||||
|
("TXPIPPMOVRDEN", 1),
|
||||||
|
("TXPIPPMPD", 1),
|
||||||
|
("TXPIPPMSEL", 1),
|
||||||
|
("TXPISOPD", 1),
|
||||||
|
("TXPMARESET", 1),
|
||||||
|
("TXPOLARITY", 1),
|
||||||
|
("TXPOSTCURSORINV", 1),
|
||||||
|
("TXPRBSFORCEERR", 1),
|
||||||
|
("TXPRECURSORINV", 1),
|
||||||
|
("TXRATEMODE", 1),
|
||||||
|
("TXSTARTSEQ", 1),
|
||||||
|
("TXSWING", 1),
|
||||||
|
("TXSYNCALLIN", 1),
|
||||||
|
("TXSYNCIN", 1),
|
||||||
|
("TXSYNCMODE", 1),
|
||||||
|
("TXUSERRDY", 1),
|
||||||
|
("TXUSRCLK2", 1),
|
||||||
|
("TXUSRCLK", 1),
|
||||||
|
("RXADAPTSELTEST", 14),
|
||||||
|
("DRPDI", 16),
|
||||||
|
("GTRSVD", 16),
|
||||||
|
("PCSRSVDIN", 16),
|
||||||
|
("TSTIN", 20),
|
||||||
|
("RXELECIDLEMODE", 2),
|
||||||
|
("RXPD", 2),
|
||||||
|
("RXSYSCLKSEL", 2),
|
||||||
|
("TXPD", 2),
|
||||||
|
("TXSYSCLKSEL", 2),
|
||||||
|
("LOOPBACK", 3),
|
||||||
|
("RXCHBONDLEVEL", 3),
|
||||||
|
("RXOUTCLKSEL", 3),
|
||||||
|
("RXPRBSSEL", 3),
|
||||||
|
("RXRATE", 3),
|
||||||
|
("TXBUFDIFFCTRL", 3),
|
||||||
|
("TXHEADER", 3),
|
||||||
|
("TXMARGIN", 3),
|
||||||
|
("TXOUTCLKSEL", 3),
|
||||||
|
("TXPRBSSEL", 3),
|
||||||
|
("TXRATE", 3),
|
||||||
|
("TXDATA", 32),
|
||||||
|
("RXCHBONDI", 4),
|
||||||
|
("RXOSINTCFG", 4),
|
||||||
|
("RXOSINTID0", 4),
|
||||||
|
("TX8B10BBYPASS", 4),
|
||||||
|
("TXCHARDISPMODE", 4),
|
||||||
|
("TXCHARDISPVAL", 4),
|
||||||
|
("TXCHARISK", 4),
|
||||||
|
("TXDIFFCTRL", 4),
|
||||||
|
("TXPIPPMSTEPSIZE", 5),
|
||||||
|
("TXPOSTCURSOR", 5),
|
||||||
|
("TXPRECURSOR", 5),
|
||||||
|
("TXMAINCURSOR", 7),
|
||||||
|
("TXSEQUENCE", 7),
|
||||||
|
("DRPADDR", 9),
|
||||||
|
],
|
||||||
|
"GTPE2_COMMON": [
|
||||||
|
("BGBYPASSB", 1),
|
||||||
|
("BGMONITORENB", 1),
|
||||||
|
("BGPDB", 1),
|
||||||
|
("BGRCALOVRDENB", 1),
|
||||||
|
("DRPCLK", 1),
|
||||||
|
("DRPEN", 1),
|
||||||
|
("DRPWE", 1),
|
||||||
|
("PLL0LOCKDETCLK", 1),
|
||||||
|
("PLL0LOCKEN", 1),
|
||||||
|
("PLL0PD", 1),
|
||||||
|
("PLL0RESET", 1),
|
||||||
|
("PLL1LOCKDETCLK", 1),
|
||||||
|
("PLL1LOCKEN", 1),
|
||||||
|
("PLL1PD", 1),
|
||||||
|
("PLL1RESET", 1),
|
||||||
|
("RCALENB", 1),
|
||||||
|
("DRPDI", 16),
|
||||||
|
("PLLRSVD1", 16),
|
||||||
|
("PLL0REFCLKSEL", 3),
|
||||||
|
("PLL1REFCLKSEL", 3),
|
||||||
|
("BGRCALOVRD", 5),
|
||||||
|
("PLLRSVD2", 5),
|
||||||
|
("DRPADDR", 8),
|
||||||
|
("PMARSVD", 8),
|
||||||
|
],
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
#!/usr/bin/env python3
|
||||||
|
# -*- coding: utf-8 -*-
|
||||||
|
#
|
||||||
|
# Copyright (C) 2017-2020 The Project X-Ray Authors.
|
||||||
|
#
|
||||||
|
# Use of this source code is governed by a ISC-style
|
||||||
|
# license that can be found in the LICENSE file or at
|
||||||
|
# https://opensource.org/licenses/ISC
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: ISC
|
||||||
|
import os
|
||||||
|
import random
|
||||||
|
import math
|
||||||
|
random.seed(int(os.getenv("SEED"), 16))
|
||||||
|
from prjxray import util
|
||||||
|
from prjxray.lut_maker import LutMaker
|
||||||
|
from prjxray.db import Database
|
||||||
|
|
||||||
|
from ports import ports
|
||||||
|
|
||||||
|
|
||||||
|
def print_site(ports, luts, site, site_type):
|
||||||
|
verilog_ports = ""
|
||||||
|
verilog_wires = ""
|
||||||
|
|
||||||
|
for port, width in ports:
|
||||||
|
verilog_ports += """
|
||||||
|
.{port}({port}_{site}),""".format(
|
||||||
|
port=port, site=site)
|
||||||
|
verilog_wires += "wire [{}:0] {}_{};\n".format(width - 1, port, site)
|
||||||
|
|
||||||
|
for idx in range(0, width):
|
||||||
|
verilog_wires += "assign {}_{}[{}] = {};\n".format(
|
||||||
|
port, site, idx, luts.get_next_output_net())
|
||||||
|
|
||||||
|
verilog_wires += "\n"
|
||||||
|
|
||||||
|
verilog_ports = verilog_ports.rstrip(",")
|
||||||
|
|
||||||
|
print(
|
||||||
|
"""
|
||||||
|
{wires}
|
||||||
|
|
||||||
|
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||||
|
{site_type} {site}_instance (
|
||||||
|
{ports}
|
||||||
|
);""".format(
|
||||||
|
wires=verilog_wires,
|
||||||
|
ports=verilog_ports,
|
||||||
|
site=site,
|
||||||
|
site_type=site_type))
|
||||||
|
|
||||||
|
|
||||||
|
def main():
|
||||||
|
db = Database(util.get_db_root(), util.get_part())
|
||||||
|
grid = db.grid()
|
||||||
|
|
||||||
|
luts = LutMaker()
|
||||||
|
|
||||||
|
def gen_sites(desired_site_type):
|
||||||
|
for tile_name in sorted(grid.tiles()):
|
||||||
|
loc = grid.loc_of_tilename(tile_name)
|
||||||
|
gridinfo = grid.gridinfo_at_loc(loc)
|
||||||
|
for site, site_type in gridinfo.sites.items():
|
||||||
|
if site_type == desired_site_type:
|
||||||
|
yield tile_name, site
|
||||||
|
|
||||||
|
print('''
|
||||||
|
module top();
|
||||||
|
|
||||||
|
(* KEEP, DONT_TOUCH *)
|
||||||
|
LUT6 dummy();
|
||||||
|
''')
|
||||||
|
|
||||||
|
for site_type in ["GTPE2_CHANNEL", "GTPE2_COMMON"]:
|
||||||
|
for _, site in gen_sites(site_type):
|
||||||
|
print_site(ports[site_type], luts, site, site_type)
|
||||||
|
|
||||||
|
for l in luts.create_wires_and_luts():
|
||||||
|
print(l)
|
||||||
|
|
||||||
|
print('endmodule')
|
||||||
|
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
|
|
@ -161,6 +161,7 @@ $(eval $(call fuzzer,061-pcie-conf,005-tilegrid,all))
|
||||||
$(eval $(call fuzzer,063-gtp-common-conf,005-tilegrid,part))
|
$(eval $(call fuzzer,063-gtp-common-conf,005-tilegrid,part))
|
||||||
$(eval $(call fuzzer,064-gtp-channel-conf,005-tilegrid,part))
|
$(eval $(call fuzzer,064-gtp-channel-conf,005-tilegrid,part))
|
||||||
$(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part))
|
$(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part))
|
||||||
|
$(eval $(call fuzzer,066-gtp-int-pips,005-tilegrid,all))
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
|
||||||
|
|
@ -379,6 +379,8 @@ class Segmaker:
|
||||||
tile_type_norm = 'GTP_CHANNEL'
|
tile_type_norm = 'GTP_CHANNEL'
|
||||||
if 'GTP_COMMON' in tile_type_norm:
|
if 'GTP_COMMON' in tile_type_norm:
|
||||||
tile_type_norm = 'GTP_COMMON'
|
tile_type_norm = 'GTP_COMMON'
|
||||||
|
if 'GTP_INT_INTERFACE' in tile_type_norm:
|
||||||
|
tile_type_norm = 'GTP_INT_INTERFACE'
|
||||||
|
|
||||||
# ignore dummy tiles (ex: VBRK)
|
# ignore dummy tiles (ex: VBRK)
|
||||||
if len(tiledata['bits']) == 0:
|
if len(tiledata['bits']) == 0:
|
||||||
|
|
|
||||||
|
|
@ -205,6 +205,15 @@ case "$1" in
|
||||||
gtp_channel_3_mid_right)
|
gtp_channel_3_mid_right)
|
||||||
sed < "$2" > "$tmp1" -e 's/^GTP_CHANNEL\./GTP_CHANNEL_3_MID_RIGHT./' ;;
|
sed < "$2" > "$tmp1" -e 's/^GTP_CHANNEL\./GTP_CHANNEL_3_MID_RIGHT./' ;;
|
||||||
|
|
||||||
|
gtp_int_interface_l)
|
||||||
|
sed < "$2" > "$tmp1" -e 's/^GTP_INT_INTERFACE\.GTPE2_INT/GTP_INT_INTERFACE_L\.GTPE2_INT_LEFT/' ;;
|
||||||
|
|
||||||
|
gtp_int_interface_r)
|
||||||
|
sed < "$2" > "$tmp1" -e 's/^GTP_INT_INTERFACE\.GTPE2_INT/GTP_INT_INTERFACE_R\.GTPE2_INT_R/' ;;
|
||||||
|
|
||||||
|
gtp_int_interface)
|
||||||
|
cp "$2" "$tmp1" ;;
|
||||||
|
|
||||||
mask_*)
|
mask_*)
|
||||||
db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
|
db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
|
||||||
ismask=true
|
ismask=true
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue