diff --git a/fuzzers/066-gtp-int-pips/Makefile b/fuzzers/066-gtp-int-pips/Makefile new file mode 100644 index 00000000..3f34edf0 --- /dev/null +++ b/fuzzers/066-gtp-int-pips/Makefile @@ -0,0 +1,55 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +export FUZDIR=$(shell pwd) +PIP_TYPE?=gtp_int_interface +SEG_TYPE?=gtp_int_interface +PIPLIST_TCL=$(FUZDIR)/gtp_int_interface_pip_list.tcl + +BUILD_DIR = build +RUN_OK = run.ok + +TODO_RE=".*" + +MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(SEG_TYPE) --re $(TODO_RE) --sides "" +N = 2 + +SEGMATCH_FLAGS=-c 1 + +A_PIPLIST=gtp_int_interface.txt + +CHECK_ARGS= --zero-entries --timeout-iters 2 + +include ../pip_loop.mk + +$(BUILD_DIR)/segbits_gtp_int_interface.rdb: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_gtp_int_interface.rdb \ + $(shell find $(BUILD_DIR) -name segdata_gtp_int_interface*.txt) + +RDBS = $(BUILD_DIR)/segbits_gtp_int_interface.rdb + +database: ${RDBS} + ${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \ + --seg-fn-in $(BUILD_DIR)/segbits_gtp_int_interface.rdb \ + --seg-fn-out $(BUILD_DIR)/segbits_gtp_int_interface.db + + # Keep a copy to track iter progress + cp $(BUILD_DIR)/segbits_gtp_int_interface.rdb $(BUILD_DIR)/$(ITER)/segbits_gtp_int_interface.rdb + cp $(BUILD_DIR)/segbits_gtp_int_interface.db $(BUILD_DIR)/$(ITER)/segbits_gtp_int_interface.db + + # Clobber existing .db to eliminate potential conflicts + cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db $(BUILD_DIR)/database/${XRAY_DATABASE} + XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} gtp_int_interface_l $(BUILD_DIR)/segbits_gtp_int_interface.db + XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} gtp_int_interface_r $(BUILD_DIR)/segbits_gtp_int_interface.db + XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} gtp_int_interface $(BUILD_DIR)/segbits_gtp_int_interface.db + +pushdb: database + ${XRAY_MERGEDB} gtp_int_interface_l $(BUILD_DIR)/segbits_gtp_int_interface.db + ${XRAY_MERGEDB} gtp_int_interface_r $(BUILD_DIR)/segbits_gtp_int_interface.db + ${XRAY_MERGEDB} gtp_int_interface $(BUILD_DIR)/segbits_gtp_int_interface.db + +.PHONY: database pushdb run clean diff --git a/fuzzers/066-gtp-int-pips/bits.dbf b/fuzzers/066-gtp-int-pips/bits.dbf new file mode 100644 index 00000000..e69de29b diff --git a/fuzzers/066-gtp-int-pips/generate.py b/fuzzers/066-gtp-int-pips/generate.py new file mode 100644 index 00000000..8bcc69fa --- /dev/null +++ b/fuzzers/066-gtp-int-pips/generate.py @@ -0,0 +1,99 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC + +from prjxray.segmaker import Segmaker +import os +import os.path + + +def bitfilter(frame, word): + word = int(word / 32) + + if frame not in [26, 27]: + return False + + return True + + +def read_pip_data(pipfile, pipdata, tile_ports): + with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build', + 'gtp_int_interface', pipfile)) as f: + for l in f: + tile_type, dst, src = l.strip().split('.') + if tile_type not in pipdata: + pipdata[tile_type] = [] + tile_ports[tile_type] = set() + + pipdata[tile_type].append((src, dst)) + tile_ports[tile_type].add(src) + tile_ports[tile_type].add(dst) + + +def main(): + segmk = Segmaker("design.bits") + + tiledata = {} + pipdata = {} + ignpip = set() + tile_ports = {} + + read_pip_data('gtp_int_interface.txt', pipdata, tile_ports) + + print("Loading tags from design.txt.") + with open("design.txt", "r") as f: + for line in f: + tile, pip, src, dst, pnum, pdir = line.split() + + if not tile.startswith('GTP_INT_INTERFACE'): + continue + + pip_prefix, _ = pip.split(".") + tile_from_pip, tile_type = pip_prefix.split('/') + assert tile == tile_from_pip + _, src = src.split("/") + _, dst = dst.split("/") + pnum = int(pnum) + pdir = int(pdir) + + if tile not in tiledata: + tiledata[tile] = { + "type": tile_type, + "pips": set(), + "srcs": set(), + "dsts": set() + } + + tiledata[tile]["pips"].add((src, dst)) + tiledata[tile]["srcs"].add(src) + tiledata[tile]["dsts"].add(dst) + + if pdir == 0: + tiledata[tile]["srcs"].add(dst) + tiledata[tile]["dsts"].add(src) + + for tile, pips_srcs_dsts in tiledata.items(): + tile_type = pips_srcs_dsts["type"] + pips = pips_srcs_dsts["pips"] + + for src, dst in pipdata["GTP_INT_INTERFACE"]: + if (src, dst) in ignpip: + pass + elif (src, dst) in pips: + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1) + else: + segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0) + + segmk.compile(bitfilter=bitfilter) + segmk.write() + + +if __name__ == "__main__": + main() diff --git a/fuzzers/066-gtp-int-pips/generate.tcl b/fuzzers/066-gtp-int-pips/generate.tcl new file mode 100644 index 00000000..13e2e9bc --- /dev/null +++ b/fuzzers/066-gtp-int-pips/generate.tcl @@ -0,0 +1,67 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc route_delay {} { + set nets [get_nets] + + foreach net $nets { + set wire [get_wires -of_objects $net -filter { TILE_NAME =~ "*GTP_INT_INTERFACE*" && NAME =~ "*IMUX_OUT*" }] + + if { $wire == "" } { + continue + } + + if { rand() < 0.60 } { + continue + } + + set parts [split $wire "/"] + set tile_name [lindex $parts 0] + set wire_name [lindex $parts 1] + + set delay_wire_name [string map {OUT DELAY} $wire_name] + set delay_node [get_nodes $tile_name/$delay_wire_name] + + if { $delay_node == "" } { + exit 1 + } + + route_design -unroute -nets $net + puts "Attempting to route net $net through $delay_node." + route_via $net [list $delay_node] + } +} + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + + set_property IS_ENABLED 0 [get_drc_checks {REQP-47}] + set_property IS_ENABLED 0 [get_drc_checks {REQP-48}] + + set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets] + + place_design -directive Quick + route_design -directive Quick + + route_delay + + route_design + + write_checkpoint -force design.dcp + write_bitstream -force design.bit + write_pip_txtdata design.txt +} + +run diff --git a/fuzzers/066-gtp-int-pips/gtp_int_interface_pip_list.tcl b/fuzzers/066-gtp-int-pips/gtp_int_interface_pip_list.tcl new file mode 100644 index 00000000..ca7a56d9 --- /dev/null +++ b/fuzzers/066-gtp-int-pips/gtp_int_interface_pip_list.tcl @@ -0,0 +1,47 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +proc print_tile_pips {tile_type filename} { + set fp [open $filename w] + set pips [dict create] + foreach tile [get_tiles -filter "TYPE =~ $tile_type*"] { + foreach pip [lsort [get_pips -of_objects $tile]] { + set src [get_wires -uphill -of_objects $pip] + set dst [get_wires -downhill -of_objects $pip] + + # Skip pips with disconnected nodes + set src_node [get_nodes -of_objects $src] + + if { $src_node == {} } { + continue + } + + set dst_node [get_nodes -of_objects $dst] + if { $dst_node == {} } { + continue + } + + set src_wire [regsub {.*/} $src ""] + set src_delay_match [regexp {DELAY} $src_wire] + + if { $src_delay_match } { + set pip_string "GTP_INT_INTERFACE.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]" + if ![dict exists $pips $pip_string] { + puts $fp $pip_string + dict set pips $pip_string 1 + } + } + } + } + close $fp +} + +create_project -force -part $::env(XRAY_PART) design design +set_property design_mode PinPlanning [current_fileset] +open_io_design -name io_1 + +print_tile_pips GTP_INT_INTERFACE gtp_int_interface.txt diff --git a/fuzzers/066-gtp-int-pips/ports.py b/fuzzers/066-gtp-int-pips/ports.py new file mode 100644 index 00000000..0c17f7dc --- /dev/null +++ b/fuzzers/066-gtp-int-pips/ports.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC + +ports = { + "GTPE2_CHANNEL": [ + ("CFGRESET", 1), + ("CLKRSVD0", 1), + ("CLKRSVD1", 1), + ("DMONFIFORESET", 1), + ("DMONITORCLK", 1), + ("DRPCLK", 1), + ("DRPEN", 1), + ("DRPWE", 1), + ("EYESCANMODE", 1), + ("EYESCANRESET", 1), + ("EYESCANTRIGGER", 1), + ("GTRESETSEL", 1), + ("GTRXRESET", 1), + ("GTTXRESET", 1), + ("PMARSVDIN0", 1), + ("PMARSVDIN1", 1), + ("PMARSVDIN2", 1), + ("PMARSVDIN3", 1), + ("PMARSVDIN4", 1), + ("RESETOVRD", 1), + ("RX8B10BEN", 1), + ("RXBUFRESET", 1), + ("RXCDRFREQRESET", 1), + ("RXCDRHOLD", 1), + ("RXCDROVRDEN", 1), + ("RXCDRRESET", 1), + ("RXCDRRESETRSV", 1), + ("RXCHBONDEN", 1), + ("RXCHBONDMASTER", 1), + ("RXCHBONDSLAVE", 1), + ("RXCOMMADETEN", 1), + ("RXDDIEN", 1), + ("RXDFEXYDEN", 1), + ("RXDLYBYPASS", 1), + ("RXDLYEN", 1), + ("RXDLYOVRDEN", 1), + ("RXDLYSRESET", 1), + ("RXGEARBOXSLIP", 1), + ("RXLPMHFHOLD", 1), + ("RXLPMHFOVRDEN", 1), + ("RXLPMLFHOLD", 1), + ("RXLPMLFOVRDEN", 1), + ("RXLPMOSINTNTRLEN", 1), + ("RXLPMRESET", 1), + ("RXMCOMMAALIGNEN", 1), + ("RXOOBRESET", 1), + ("RXOSCALRESET", 1), + ("RXOSHOLD", 1), + ("RXOSINTEN", 1), + ("RXOSINTHOLD", 1), + ("RXOSINTNTRLEN", 1), + ("RXOSINTOVRDEN", 1), + ("RXOSINTPD", 1), + ("RXOSINTSTROBE", 1), + ("RXOSINTTESTOVRDEN", 1), + ("RXOSOVRDEN", 1), + ("RXPCOMMAALIGNEN", 1), + ("RXPCSRESET", 1), + ("RXPHALIGN", 1), + ("RXPHALIGNEN", 1), + ("RXPHDLYPD", 1), + ("RXPHDLYRESET", 1), + ("RXPHOVRDEN", 1), + ("RXPMARESET", 1), + ("RXPOLARITY", 1), + ("RXPRBSCNTRESET", 1), + ("RXRATEMODE", 1), + ("RXSLIDE", 1), + ("RXSYNCALLIN", 1), + ("RXSYNCIN", 1), + ("RXSYNCMODE", 1), + ("RXUSERRDY", 1), + ("RXUSRCLK2", 1), + ("RXUSRCLK", 1), + ("SETERRSTATUS", 1), + ("SIGVALIDCLK", 1), + ("TX8B10BEN", 1), + ("TXCOMINIT", 1), + ("TXCOMSAS", 1), + ("TXCOMWAKE", 1), + ("TXDEEMPH", 1), + ("TXDETECTRX", 1), + ("TXDIFFPD", 1), + ("TXDLYBYPASS", 1), + ("TXDLYEN", 1), + ("TXDLYHOLD", 1), + ("TXDLYOVRDEN", 1), + ("TXDLYSRESET", 1), + ("TXDLYUPDOWN", 1), + ("TXELECIDLE", 1), + ("TXINHIBIT", 1), + ("TXPCSRESET", 1), + ("TXPDELECIDLEMODE", 1), + ("TXPHALIGN", 1), + ("TXPHALIGNEN", 1), + ("TXPHDLYPD", 1), + ("TXPHDLYRESET", 1), + ("TXPHDLYTSTCLK", 1), + ("TXPHINIT", 1), + ("TXPHOVRDEN", 1), + ("TXPIPPMEN", 1), + ("TXPIPPMOVRDEN", 1), + ("TXPIPPMPD", 1), + ("TXPIPPMSEL", 1), + ("TXPISOPD", 1), + ("TXPMARESET", 1), + ("TXPOLARITY", 1), + ("TXPOSTCURSORINV", 1), + ("TXPRBSFORCEERR", 1), + ("TXPRECURSORINV", 1), + ("TXRATEMODE", 1), + ("TXSTARTSEQ", 1), + ("TXSWING", 1), + ("TXSYNCALLIN", 1), + ("TXSYNCIN", 1), + ("TXSYNCMODE", 1), + ("TXUSERRDY", 1), + ("TXUSRCLK2", 1), + ("TXUSRCLK", 1), + ("RXADAPTSELTEST", 14), + ("DRPDI", 16), + ("GTRSVD", 16), + ("PCSRSVDIN", 16), + ("TSTIN", 20), + ("RXELECIDLEMODE", 2), + ("RXPD", 2), + ("RXSYSCLKSEL", 2), + ("TXPD", 2), + ("TXSYSCLKSEL", 2), + ("LOOPBACK", 3), + ("RXCHBONDLEVEL", 3), + ("RXOUTCLKSEL", 3), + ("RXPRBSSEL", 3), + ("RXRATE", 3), + ("TXBUFDIFFCTRL", 3), + ("TXHEADER", 3), + ("TXMARGIN", 3), + ("TXOUTCLKSEL", 3), + ("TXPRBSSEL", 3), + ("TXRATE", 3), + ("TXDATA", 32), + ("RXCHBONDI", 4), + ("RXOSINTCFG", 4), + ("RXOSINTID0", 4), + ("TX8B10BBYPASS", 4), + ("TXCHARDISPMODE", 4), + ("TXCHARDISPVAL", 4), + ("TXCHARISK", 4), + ("TXDIFFCTRL", 4), + ("TXPIPPMSTEPSIZE", 5), + ("TXPOSTCURSOR", 5), + ("TXPRECURSOR", 5), + ("TXMAINCURSOR", 7), + ("TXSEQUENCE", 7), + ("DRPADDR", 9), + ], + "GTPE2_COMMON": [ + ("BGBYPASSB", 1), + ("BGMONITORENB", 1), + ("BGPDB", 1), + ("BGRCALOVRDENB", 1), + ("DRPCLK", 1), + ("DRPEN", 1), + ("DRPWE", 1), + ("PLL0LOCKDETCLK", 1), + ("PLL0LOCKEN", 1), + ("PLL0PD", 1), + ("PLL0RESET", 1), + ("PLL1LOCKDETCLK", 1), + ("PLL1LOCKEN", 1), + ("PLL1PD", 1), + ("PLL1RESET", 1), + ("RCALENB", 1), + ("DRPDI", 16), + ("PLLRSVD1", 16), + ("PLL0REFCLKSEL", 3), + ("PLL1REFCLKSEL", 3), + ("BGRCALOVRD", 5), + ("PLLRSVD2", 5), + ("DRPADDR", 8), + ("PMARSVD", 8), + ], +} diff --git a/fuzzers/066-gtp-int-pips/top.py b/fuzzers/066-gtp-int-pips/top.py new file mode 100644 index 00000000..021f2f62 --- /dev/null +++ b/fuzzers/066-gtp-int-pips/top.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +import os +import random +import math +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray.lut_maker import LutMaker +from prjxray.db import Database + +from ports import ports + + +def print_site(ports, luts, site, site_type): + verilog_ports = "" + verilog_wires = "" + + for port, width in ports: + verilog_ports += """ + .{port}({port}_{site}),""".format( + port=port, site=site) + verilog_wires += "wire [{}:0] {}_{};\n".format(width - 1, port, site) + + for idx in range(0, width): + verilog_wires += "assign {}_{}[{}] = {};\n".format( + port, site, idx, luts.get_next_output_net()) + + verilog_wires += "\n" + + verilog_ports = verilog_ports.rstrip(",") + + print( + """ +{wires} + +(* KEEP, DONT_TOUCH, LOC = "{site}" *) +{site_type} {site}_instance ( +{ports} +);""".format( + wires=verilog_wires, + ports=verilog_ports, + site=site, + site_type=site_type)) + + +def main(): + db = Database(util.get_db_root(), util.get_part()) + grid = db.grid() + + luts = LutMaker() + + def gen_sites(desired_site_type): + for tile_name in sorted(grid.tiles()): + loc = grid.loc_of_tilename(tile_name) + gridinfo = grid.gridinfo_at_loc(loc) + for site, site_type in gridinfo.sites.items(): + if site_type == desired_site_type: + yield tile_name, site + + print(''' +module top(); + + (* KEEP, DONT_TOUCH *) + LUT6 dummy(); +''') + + for site_type in ["GTPE2_CHANNEL", "GTPE2_COMMON"]: + for _, site in gen_sites(site_type): + print_site(ports[site_type], luts, site, site_type) + + for l in luts.create_wires_and_luts(): + print(l) + + print('endmodule') + + +if __name__ == "__main__": + main() diff --git a/fuzzers/Makefile b/fuzzers/Makefile index e00fde32..4132fe72 100644 --- a/fuzzers/Makefile +++ b/fuzzers/Makefile @@ -161,6 +161,7 @@ $(eval $(call fuzzer,061-pcie-conf,005-tilegrid,all)) $(eval $(call fuzzer,063-gtp-common-conf,005-tilegrid,part)) $(eval $(call fuzzer,064-gtp-channel-conf,005-tilegrid,part)) $(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part)) +$(eval $(call fuzzer,066-gtp-int-pips,005-tilegrid,all)) endif endif endif diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py index a6503351..2c162827 100644 --- a/prjxray/segmaker.py +++ b/prjxray/segmaker.py @@ -379,6 +379,8 @@ class Segmaker: tile_type_norm = 'GTP_CHANNEL' if 'GTP_COMMON' in tile_type_norm: tile_type_norm = 'GTP_COMMON' + if 'GTP_INT_INTERFACE' in tile_type_norm: + tile_type_norm = 'GTP_INT_INTERFACE' # ignore dummy tiles (ex: VBRK) if len(tiledata['bits']) == 0: diff --git a/utils/mergedb.sh b/utils/mergedb.sh index 85a3193c..c3eaef57 100755 --- a/utils/mergedb.sh +++ b/utils/mergedb.sh @@ -205,6 +205,15 @@ case "$1" in gtp_channel_3_mid_right) sed < "$2" > "$tmp1" -e 's/^GTP_CHANNEL\./GTP_CHANNEL_3_MID_RIGHT./' ;; + gtp_int_interface_l) + sed < "$2" > "$tmp1" -e 's/^GTP_INT_INTERFACE\.GTPE2_INT/GTP_INT_INTERFACE_L\.GTPE2_INT_LEFT/' ;; + + gtp_int_interface_r) + sed < "$2" > "$tmp1" -e 's/^GTP_INT_INTERFACE\.GTPE2_INT/GTP_INT_INTERFACE_R\.GTPE2_INT_R/' ;; + + gtp_int_interface) + cp "$2" "$tmp1" ;; + mask_*) db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db ismask=true