From 4c2b0a539551c7e4fb5c3e6ba601c83139deb9fe Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 26 Jun 2019 13:19:57 +0200 Subject: [PATCH] Added minitests for SRLs Signed-off-by: Maciej Kurc --- minitests/srl/Makefile | 45 ++++++++++++++++++++++++++++ minitests/srl/README.md | 5 ++++ minitests/srl/par.tcl | 36 ++++++++++++++++++++++ minitests/srl/srl32_init.v | 25 ++++++++++++++++ minitests/srl/srl32_x1.v | 21 +++++++++++++ minitests/srl/srl32_x2.v | 31 +++++++++++++++++++ minitests/srl/srl32_x2_chain.v | 33 ++++++++++++++++++++ minitests/srl/srl32_x3.v | 41 +++++++++++++++++++++++++ minitests/srl/srl32_x3_chain.v | 44 +++++++++++++++++++++++++++ minitests/srl/srl32_x4.v | 51 +++++++++++++++++++++++++++++++ minitests/srl/srl32_x4_chain.v | 55 ++++++++++++++++++++++++++++++++++ 11 files changed, 387 insertions(+) create mode 100644 minitests/srl/Makefile create mode 100644 minitests/srl/README.md create mode 100644 minitests/srl/par.tcl create mode 100644 minitests/srl/srl32_init.v create mode 100644 minitests/srl/srl32_x1.v create mode 100644 minitests/srl/srl32_x2.v create mode 100644 minitests/srl/srl32_x2_chain.v create mode 100644 minitests/srl/srl32_x3.v create mode 100644 minitests/srl/srl32_x3_chain.v create mode 100644 minitests/srl/srl32_x4.v create mode 100644 minitests/srl/srl32_x4_chain.v diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile new file mode 100644 index 00000000..bbccc9e2 --- /dev/null +++ b/minitests/srl/Makefile @@ -0,0 +1,45 @@ +YOSYS = $(XRAY_DIR)/third_party/yosys/yosys +PART = xc7a35tcsg324-1 +BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose + +VERILOG_FILES = $(wildcard *.v) +FASM_TARGETS = $(VERILOG_FILES:.v=.fasm) +SEGPRINT_TARGETS = $(VERILOG_FILES:.v=.segprint.log) + +all: $(FASM_TARGETS) $(SEGPRINT_TARGETS) + +clean: + @find . -name "build.*" | xargs rm -rf + @rm -f *.edif + @rm -f *.bit + @rm -f *.bin + @rm -f *.bits + @rm -f *.fasm + @rm -f *.log + @rm -f *.dcp + +.PHONY: all clean + +$(YOSYS): + cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) + +%.edif: %.v $(YOSYS) + $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log + +%.bit: %.edif par.tcl + mkdir -p build.$(basename $@) + cd build.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +%.fasm: %.bit + PYTHONPATH="$(XRAY_DIR):$(XRAY_DIR)/utils:$(XRAY_DIR)/third_party/fasm" \ + PATH="$(XRAY_DIR)/build/tools:$(PATH)" \ + $(XRAY_BIT2FASM) $(BIT2FASM_ARGS) \ + $< >$@ \ + || (rm -f $@ && exit 1) + +%.bits: %.bit + $(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART).yaml -o $@ -z -y $< + +%.segprint.log: %.bits + $(XRAY_SEGPRINT) -z -D -b $< > $@ diff --git a/minitests/srl/README.md b/minitests/srl/README.md new file mode 100644 index 00000000..c634fe1a --- /dev/null +++ b/minitests/srl/README.md @@ -0,0 +1,5 @@ +# Minitests for SRLs + +This is a minitest for various SRL configurations. + +Uses Yosys to generate EDIF which is then P&R'd by Vivado. The makefile also invokes bit2fasm and segprint \ No newline at end of file diff --git a/minitests/srl/par.tcl b/minitests/srl/par.tcl new file mode 100644 index 00000000..b0f9eae4 --- /dev/null +++ b/minitests/srl/par.tcl @@ -0,0 +1,36 @@ +create_project -force -name $env(PROJECT_NAME) -part xc7a35ticsg324-1L + +#read_xdc ../top.xdc +read_edif ../$env(PROJECT_NAME).edif + +link_design -part xc7a35ticsg324-1L + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +opt_design +place_design + +report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt +report_utilization -file top_utilization_place.rpt +report_io -file top_io.rpt +report_control_sets -verbose -file top_control_sets.rpt +report_clock_utilization -file top_clock_utilization.rpt + +route_design +#phys_opt_design + +report_timing_summary -no_header -no_detailed_paths + +write_checkpoint -force ../$env(PROJECT_NAME).dcp + +set_property SEVERITY {Warning} [get_drc_checks UCIO-1] +set_property SEVERITY {Warning} [get_drc_checks NSTD-1] + +report_route_status -file top_route_status.rpt +report_drc -file top_drc.rpt +report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt +report_power -file top_power.rpt + +write_bitstream -force ../$env(PROJECT_NAME).bit diff --git a/minitests/srl/srl32_init.v b/minitests/srl/srl32_init.v new file mode 100644 index 00000000..b80a6ec7 --- /dev/null +++ b/minitests/srl/srl32_init.v @@ -0,0 +1,25 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E # + ( + .INIT(32'hF0F01030) + ) + srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x1.v b/minitests/srl/srl32_x1.v new file mode 100644 index 00000000..2d309662 --- /dev/null +++ b/minitests/srl/srl32_x1.v @@ -0,0 +1,21 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x2.v b/minitests/srl/srl32_x2.v new file mode 100644 index 00000000..14218c9e --- /dev/null +++ b/minitests/srl/srl32_x2.v @@ -0,0 +1,31 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire [1:0] Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]) + ); + +endmodule diff --git a/minitests/srl/srl32_x2_chain.v b/minitests/srl/srl32_x2_chain.v new file mode 100644 index 00000000..75530579 --- /dev/null +++ b/minitests/srl/srl32_x2_chain.v @@ -0,0 +1,33 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + wire q31_d; + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q31 (q31_d) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (q31_d), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x3.v b/minitests/srl/srl32_x3.v new file mode 100644 index 00000000..b36e27b4 --- /dev/null +++ b/minitests/srl/srl32_x3.v @@ -0,0 +1,41 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire [2:0] Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[2]) + ); + +endmodule diff --git a/minitests/srl/srl32_x3_chain.v b/minitests/srl/srl32_x3_chain.v new file mode 100644 index 00000000..8ead2e76 --- /dev/null +++ b/minitests/srl/srl32_x3_chain.v @@ -0,0 +1,44 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + wire q31_d; + wire q31_c; + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q31 (q31_d) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (q31_d), + .A (A), + .Q31 (q31_c) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (q31_c), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x4.v b/minitests/srl/srl32_x4.v new file mode 100644 index 00000000..9e69b7f0 --- /dev/null +++ b/minitests/srl/srl32_x4.v @@ -0,0 +1,51 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire [3:0] Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[2]) + ); + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[3]) + ); + +endmodule diff --git a/minitests/srl/srl32_x4_chain.v b/minitests/srl/srl32_x4_chain.v new file mode 100644 index 00000000..257a8d03 --- /dev/null +++ b/minitests/srl/srl32_x4_chain.v @@ -0,0 +1,55 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + wire q31_d; + wire q31_c; + wire q31_b; + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q31 (q31_d) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (q31_d), + .A (A), + .Q31 (q31_c) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (q31_c), + .A (A), + .Q (q31_b) + ); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (q31_b), + .A (A), + .Q (Q) + ); + +endmodule