From 457c0cde6f467af0d30bb08f2464d902df4d1477 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 12 Feb 2019 16:43:02 -0800
Subject: [PATCH] Make generic generate_top for tilegrid.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/005-tilegrid/bram_int/generate.tcl    | 18 +----------------
 fuzzers/005-tilegrid/cfg_int/generate.tcl     | 18 +----------------
 fuzzers/005-tilegrid/clk_bufg/generate.tcl    | 20 +------------------
 fuzzers/005-tilegrid/clk_hrow/generate.tcl    | 20 +------------------
 fuzzers/005-tilegrid/dsp/generate.tcl         | 18 +----------------
 fuzzers/005-tilegrid/fifo_int/generate.tcl    | 18 +----------------
 fuzzers/005-tilegrid/monitor_int/generate.tcl | 18 +----------------
 utils/utils.tcl                               | 17 ++++++++++++++++
 8 files changed, 24 insertions(+), 123 deletions(-)

diff --git a/fuzzers/005-tilegrid/bram_int/generate.tcl b/fuzzers/005-tilegrid/bram_int/generate.tcl
index 9e8cab8a..5a69791f 100644
--- a/fuzzers/005-tilegrid/bram_int/generate.tcl
+++ b/fuzzers/005-tilegrid/bram_int/generate.tcl
@@ -1,19 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/fuzzers/005-tilegrid/cfg_int/generate.tcl b/fuzzers/005-tilegrid/cfg_int/generate.tcl
index 9e8cab8a..5a69791f 100644
--- a/fuzzers/005-tilegrid/cfg_int/generate.tcl
+++ b/fuzzers/005-tilegrid/cfg_int/generate.tcl
@@ -1,19 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/fuzzers/005-tilegrid/clk_bufg/generate.tcl b/fuzzers/005-tilegrid/clk_bufg/generate.tcl
index 49e429ba..5a69791f 100644
--- a/fuzzers/005-tilegrid/clk_bufg/generate.tcl
+++ b/fuzzers/005-tilegrid/clk_bufg/generate.tcl
@@ -1,21 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    #set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/fuzzers/005-tilegrid/clk_hrow/generate.tcl b/fuzzers/005-tilegrid/clk_hrow/generate.tcl
index 49e429ba..5a69791f 100644
--- a/fuzzers/005-tilegrid/clk_hrow/generate.tcl
+++ b/fuzzers/005-tilegrid/clk_hrow/generate.tcl
@@ -1,21 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    #set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/fuzzers/005-tilegrid/dsp/generate.tcl b/fuzzers/005-tilegrid/dsp/generate.tcl
index 9e8cab8a..5a69791f 100644
--- a/fuzzers/005-tilegrid/dsp/generate.tcl
+++ b/fuzzers/005-tilegrid/dsp/generate.tcl
@@ -1,19 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/fuzzers/005-tilegrid/fifo_int/generate.tcl b/fuzzers/005-tilegrid/fifo_int/generate.tcl
index 9e8cab8a..5a69791f 100644
--- a/fuzzers/005-tilegrid/fifo_int/generate.tcl
+++ b/fuzzers/005-tilegrid/fifo_int/generate.tcl
@@ -1,19 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/fuzzers/005-tilegrid/monitor_int/generate.tcl b/fuzzers/005-tilegrid/monitor_int/generate.tcl
index 9e8cab8a..5a69791f 100644
--- a/fuzzers/005-tilegrid/monitor_int/generate.tcl
+++ b/fuzzers/005-tilegrid/monitor_int/generate.tcl
@@ -1,19 +1,3 @@
 source "$::env(XRAY_DIR)/utils/utils.tcl"
 
-proc run {} {
-    create_project -force -part $::env(XRAY_PART) design design
-    read_verilog top.v
-    synth_design -top top
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-    place_design
-    route_design
-
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-}
-
-run
+generate_top
diff --git a/utils/utils.tcl b/utils/utils.tcl
index cead2bab..9fea66c1 100644
--- a/utils/utils.tcl
+++ b/utils/utils.tcl
@@ -131,3 +131,20 @@ proc write_pip_txtdata {filename} {
     }
     close $fp
 }
+
+# Generic non-ROI'd generate.tcl template
+proc generate_top {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}