mirror of https://github.com/openXC7/prjxray.git
320 lines
8.3 KiB
Python
320 lines
8.3 KiB
Python
#!/usr/bin/env python3
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import argparse
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import csv
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import json
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import re
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from collections import defaultdict
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# =============================================================================
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def main():
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BUS_REGEX = re.compile("(.*[A-Z_])([0-9]+)$")
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# Parse arguments
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parser = argparse.ArgumentParser()
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parser.add_argument("csv", type=str, help="PS7 pin dump file")
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args = parser.parse_args()
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# Load pin dump
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with open(args.csv, "r") as fp:
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pin_dump = list(csv.DictReader(fp))
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# Group pins into buses
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buses = defaultdict(lambda :{
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"direction": None,
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"min": None,
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"max": None,
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"width": 0
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})
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for pin in list(pin_dump):
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# Get bus name and signal index
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match = BUS_REGEX.match(pin["name"])
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if match:
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name = match.group(1)
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idx = int(match.group(2))
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else:
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name = pin["name"]
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idx = 0
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# Get direction
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is_input = int(pin["is_input"])
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is_output = int(pin["is_output"])
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is_bidir = int(pin["is_bidir"])
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if is_input and not is_output and not is_bidir:
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direction = "input"
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elif not is_input and is_output and not is_bidir:
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direction = "output"
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elif not is_input and not is_output and is_bidir:
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direction = "inout"
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else:
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assert False, pin
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# Add to bus
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bus = buses[name]
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if bus["direction"] is None:
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bus["direction"] = direction
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else:
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assert bus["direction"] == direction
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if bus["min"] is None:
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bus["min"] = idx
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else:
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bus["min"] = min(bus["min"], idx)
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if bus["max"] is None:
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bus["max"] = idx
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else:
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bus["max"] = max(bus["max"], idx)
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bus["width"] = bus["max"] - bus["min"] + 1
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# Sort buses by their purpose
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for name, bus in buses.items():
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# A test pin (unconnected)
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if name.startswith("TEST"):
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cls = "test"
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# A debug pin (unconnected)
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elif name.startswith("DEBUG"):
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cls = "debug"
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# A MIO/DDR pin.
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elif name.startswith("MIO") or name.startswith("DDR") and \
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name != "DDRARB":
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cls = "mio"
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# PS7 clock/reset
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elif name in ["PSCLK", "PSPORB", "PSSRSTB"]:
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cls = "mio"
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# "Normal" pin
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else:
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cls = "normal"
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bus["class"] = cls
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# .....................................................
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# Generate JSON with PS7 pins grouped by direction
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ps7_pins = {"input": [], "output": [], "inout": []}
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal", "mio"]:
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continue
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if bus["width"] > 1:
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for i in range(bus["min"], bus["max"]+1):
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pin_name = "{}{}".format(name, i)
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ps7_pins[bus["direction"]].append(pin_name)
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else:
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ps7_pins[bus["direction"]].append(name)
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with open("ps7_pins.json", "w") as fp:
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json.dump(ps7_pins, fp, sort_keys=True, indent=2)
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# .....................................................
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# Generate XML model
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pb_name = "PS7"
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blif_model = "PS7_VPR"
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model_xml = """<models>
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<model name="{}">
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""".format(blif_model)
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# Inputs
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model_xml += """ <input_ports>
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"""
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal"]:
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continue
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if bus["direction"] != "input":
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continue
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model_xml += " <port name=\"{}\"/>\n".format(name)
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# Outputs
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model_xml += """ </input_ports>
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<output_ports>
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"""
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal"]:
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continue
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if bus["direction"] != "output":
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continue
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model_xml += " <port name=\"{}\"/>\n".format(name)
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model_xml += """ </output_ports>
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"""
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model_xml += """ </model>
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</models>"""
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with open("ps7.model.xml", "w") as fp:
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fp.write(model_xml)
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# .....................................................
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# Generate XML pb_type
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pb_xml = """<pb_type name="{}" blif_model=".subckt {}" num_pb="1">
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""".format(pb_name, blif_model)
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal"]:
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continue
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pb_xml += " <{} name=\"{}\" num_pins=\"{}\"/>\n".format(
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bus["direction"].ljust(6), name, bus["width"])
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pb_xml += """</pb_type>
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"""
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with open("ps7.pb_type.xml", "w") as fp:
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fp.write(pb_xml)
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# .....................................................
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# Prepare Verilog module definition for the PS7_VPR
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port_defs = []
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins (eg. MIO and DDR)
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if bus["class"] not in ["normal"]:
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continue
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# Generate port definition
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if bus["width"] > 1:
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port_str = " {} [{:>2d}:{:>2d}] {}".format(
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bus["direction"].ljust(6), bus["max"], bus["min"], name)
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else:
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port_str = " {} {}".format(
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bus["direction"].ljust(6), name)
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port_defs.append(port_str)
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verilog = """(* blackbox *)
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module PS7_VPR (
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{}
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);
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endmodule
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""".format(",\n".join(port_defs))
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with open("ps7_sim.v", "w") as fp:
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fp.write(verilog)
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# .....................................................
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# Prepare techmap that maps PS7 to PS7_VPR and handles
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# unconnected inputs (ties them to GND)
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port_defs = []
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port_conns = []
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param_defs = []
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wire_defs = []
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal", "mio"]:
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continue
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# Generate port definition
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if bus["width"] > 1:
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port_str = " {} [{:>2d}:{:>2d}] {}".format(
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bus["direction"].ljust(6), bus["max"], bus["min"], name)
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else:
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port_str = " {} {}".format(
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bus["direction"].ljust(6), name)
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port_defs.append(port_str)
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# MIO and DDR pins are not mapped as they are dummy
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if bus["class"] == "mio":
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continue
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# This is an input port, needs to be tied to GND if unconnected
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if bus["direction"] == "input":
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# Techmap parameter definition
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param_defs.append(
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" parameter _TECHMAP_CONSTMSK_{}_ = 0;".format(name.upper()))
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param_defs.append(
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" parameter _TECHMAP_CONSTVAL_{}_ = 0;".format(name.upper()))
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# Wire definition using generate statement. Necessary for detection
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# of unconnected ports.
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wire_defs.append(
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"""
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generate if((_TECHMAP_CONSTMSK_{name_upr}_ == {N}'d0) && (_TECHMAP_CONSTVAL_{name_upr}_ == {N}'d0))
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wire [{M}:0] {name_lwr} = {N}'d0;
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else
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wire [{M}:0] {name_lwr} = {name};
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endgenerate""".format(
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name=name,
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name_upr=name.upper(),
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name_lwr=name.lower(),
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N=bus["width"],
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M=bus["width"] - 1))
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# Connection to the "generated" wire.
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port_conns.append(
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" .{name:<25}({name_lwr})".format(
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name=name, name_lwr=name.lower()))
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# An output port
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else:
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# Direct connection
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port_conns.append(" .{name:<25}({name})".format(name=name))
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# Format the final verilog.
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verilog = """module PS7 (
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{port_defs}
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);
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// Techmap specific parameters.
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{param_defs}
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// Detect all unconnected inputs and tie them to 0.
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{wire_defs}
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// Replacement cell.
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PS7_VPR _TECHMAP_REPLACE_ (
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{port_conns}
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);
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endmodule
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""".format(
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port_defs=",\n".join(port_defs),
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param_defs="\n".join(param_defs),
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wire_defs="\n".join(wire_defs),
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port_conns=",\n".join(port_conns))
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with open("ps7_map.v", "w") as fp:
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fp.write(verilog)
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# =============================================================================
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if __name__ == "__main__":
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main()
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