mirror of https://github.com/openXC7/prjxray.git
Merge pull request #66 from kc8apf/partial_reconfig_roi_rules
partial_reconfig_flow: Rework to allow any verilog for ROI
This commit is contained in:
John McMaster
GitHub
commit
414210db26
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@ -1,21 +1,23 @@
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.PRECIOUS: harness_impl.dcp %_impl.dcp %.bit
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# Top-level target for generating a programmable bitstream. Given a .fasm
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# file, calling make with the .fasm extension replaced with .hand_crafted.bit
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# file, calling make with the .fasm extension replaced with _hand_crafted.bit
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# will generate a bitstream that includes both the harness and the .fasm design
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# ready for programming to a board. For example, 'make
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# roi_noninv.hand_crafted.bit' will generate a bitstream that includes the
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# ready for programming to a board. For example,
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# 'make inv_hand_crafted.bit' will generate a bitstream that includes the
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# design from roi_noninv.fasm.
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%.hand_crafted.bit: init_sequence.bit %.no_headers.bin final_sequence.bin
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%_hand_crafted.bit: init_sequence.bit %_no_headers.bin final_sequence.bin
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cat $^ > $@
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%.no_headers.bin: %.patched.bin
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%_no_headers.bin: %_patched.bin
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -s 0x18 $< | xxd -r -p - $@
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%.patched.bin: %.frm harness_routed.bit
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%_patched.bin: %_roi_partial.frm harness.bit
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${XRAY_TOOLS_DIR}/xc7patch \
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--part_file ${XRAY_PART_YAML} \
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--bitstream_file harness_routed.bit \
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--bitstream_file harness.bit \
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--frm_file $< \
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--output_file $@
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@ -25,7 +27,7 @@
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# xc7patch-generated bitstream to create a programmable bitstream.
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#
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# The offsets used below were determined by manually inspecting
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# harness_routed.bit with a hex editor. init_sequence.bit is the beginning of
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# harness.bit with a hex editor. init_sequence.bit is the beginning of
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# the file until just before the actual frame data is sent via a write to FDRI.
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# final_sequence.bin is from just after the frame data write to the end of the
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# file. Note that final_sequence.bin normally includes at least one CRC check.
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@ -33,12 +35,12 @@
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# same behavior as setting BITSTREAM.GENERAL.CRC to Disabled. These offset
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# should not change unless you alter the bitstream format used (i.e. setting
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# BITSTREAM.GENERAL.DEBUGBITSTREAM or BITSTREAM.GENERAL.PERFRAMECRC to YES).
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init_sequence.bit: harness_routed.bit
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init_sequence.bit: harness.bit
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -l 0x147 $< | xxd -r -p - $@
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final_sequence.bin: harness_routed.bit
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final_sequence.bin: harness.bit
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# WARNING: these values need to be tweaked if anything about the
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# Vivado-generated design changes.
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xxd -p -s 0x216abf $< | \
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@ -48,29 +50,35 @@ final_sequence.bin: harness_routed.bit
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xxd -r -p - $@
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# Generate a suitable harness by using Vivado's partial reconfiguration
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# feature. roi_inv is used as a sample reconfiguration design as one is
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# feature. inv.v is used as a sample reconfiguration design as one is
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# required to generate a partial reconfiguration design.
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harness.dcp: harness.tcl top.v roi_base.v
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vivado -mode batch -source harness.tcl
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harness_synth.dcp: harness_synthesize.tcl harness.v
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vivado -mode batch -source harness_synthesize.tcl
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roi_inv.dcp: roi_inv.tcl roi_inv.v
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vivado -mode batch -source roi_inv.tcl
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harness_impl.dcp: harness_synth.dcp inv_synth.dcp harness_implement.tcl
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vivado -mode batch -source harness_implement.tcl
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roi_inv_routed.dcp roi_inv_w_harness_routed.dcp harness_routed.dcp: harness.dcp roi_inv.dcp roi_inv_routed.tcl
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vivado -mode batch -source roi_inv_routed.tcl
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# Synthesize an ROI design
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%_synth.dcp: %.v roi_synthesize.tcl
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vivado -mode batch -source roi_synthesize.tcl -tclargs $< $@
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# Implement an ROI design
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%_impl.dcp: %_synth.dcp harness_impl.dcp roi_implement.tcl
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vivado -mode batch -source roi_implement.tcl -tclargs $< $@
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# Generate bitstreams from an implemented design. Two bitstreams are
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# generated: one containing a complete design including the harness (.bit) and
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# one that only contains the frames that implement the ROI design
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# (_roi_partial.bit).
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%.bit: %_impl.dcp write_bitstream.tcl
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vivado -mode batch -source write_bitstream.tcl -tclargs $< $@
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%_roi_partial.bit: %.bit ;
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# Conversions between various formats.
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%.bit: %.dcp write_bitstream.tcl
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vivado -mode batch -source write_bitstream.tcl -tclargs $< $@
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%.bits: %.bit
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${XRAY_BITREAD} -y -o $@ $<
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${XRAY_BITREAD} -z -y -o $@ $<
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# Extract only bits that are within the ROI.
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%.roi.bits: %.bit
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${XRAY_BITREAD} -F ${XRAY_ROI_FRAMES} -z -y -o $@ $<
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%.segp: %.roi.bits
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%.segp: %.bits
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${XRAY_SEGPRINT} -zd $< > $@
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%.fasm: %.segp
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@ -85,10 +93,8 @@ roi_inv_routed.dcp roi_inv_w_harness_routed.dcp harness_routed.dcp: harness.dcp
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${XRAY_TOOLS_DIR}/bittool list_config_packets $< > $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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rm -rf out_* *~
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rm -rf *.frm *.segp *.packets *.bin
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rm -rf harness_routed.fasm roi_inv_w_harness_routed.fasm
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rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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rm -rf *.frm *.segp *.packets *.bin *.fasm
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rm -rf hd_visual
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.PHONY: clean
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@ -1,18 +1,20 @@
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# FASM Proof of Concept using Vivado Partial Reconfig flow
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top.v is a top-level design that routes a variety of signal into a black-box
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harness.v is a top-level design that routes a variety of signal into a black-box
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region of interest (ROI). Vivado's Partial Reconfiguration flow (see UG909
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and UG947) is used to implement that design and obtain a bitstream that
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configures portions of the chip that are currently undocumented.
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Designs that fit within the ROI are written in FASM and merged with the above
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harness into a bitstream with fasm2frame and xc7patch.
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harness into a bitstream with fasm2frame and xc7patch. Since writting FASM is
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rather tedious, rules are provided to convert Verilog ROI designs into FASM via
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Vivado.
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# Usage
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make rules are provided for generating each step of the process so that
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intermediate forms can be analyzed. Assuming you have a .fasm file, invoking
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the %.hand\_crafted.bit rule will generate a merged bitstream:
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the %\_hand\_crafted.bit rule will generate a merged bitstream:
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```
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make foo.hand\_crafted.bit # reads foo.fasm
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@ -21,33 +23,11 @@ make foo.hand\_crafted.bit # reads foo.fasm
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# Using Vivado to generate .fasm
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Vivado's Partial Reconfiguration flow can be used to synthesize and implement a
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design that is then converted to .fasm. The basic process is to write a module
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that _exactly_ matches the roi blackbox in the top-level design. Note that
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even the name of the module must match exactly. Once you have a design, the
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first step is to synthesize the design with -mode out\_of\_context:
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```
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read_verilog <design>.v
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synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
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write_checkpoint -force <design>.dcp
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```
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Next, implement that design within the harness. Run 'make harness\_routed.dcp'
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if it doesn't already exist. The following TCL will load the fully-routed
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harness, load your synthesized design, and generate a bitstream containing
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both:
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```
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open_checkpoint harness_routed.dcp
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read_checkpoint -cell roi <design>.dcp
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opt_design
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place_design
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route_design
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write_checkpoint -force <design>_routed.dcp
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write_bitstream -force <design>_routed.bit
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```
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'make <design>\_routed.fasm' will run a sequence of tools to extract the bits
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that are inside the ROI and convert them to FASM. The resulting .fasm can be
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used to generate a marged bitstream using
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'make <design>\_routed.hand\_crafted.bit'. The resulting bitstream should be
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equivalent to <design>\_routed.bit.
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ROI design that is then converted to .fasm. Write a Verilog module
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that _exactly_ matches the roi blackbox model in the top-level design. Note
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that even the name of the module must match exactly. Assuming you have created
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that design in my\_roi\_design.v, 'make my\_roi\_design\_hand\_crafted.bit'
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will synthesize and implement the design with Vivado, translate the resulting
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partial bitstream into FASM, and then generate a full bitstream by patching the
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harness bitstream with the FASM. non\_inv.v is provided as an example ROI
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design for this flow.
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@ -1,5 +0,0 @@
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read_verilog top.v
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read_verilog roi_base.v
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synth_design -top top -part $::env(XRAY_PART)
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write_checkpoint -force harness.dcp
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@ -1,7 +1,11 @@
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//See README and tcl for more info
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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endmodule
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module top(input wire clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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@ -1,4 +1,4 @@
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open_checkpoint harness.dcp
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open_checkpoint harness_synth.dcp
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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@ -132,18 +132,13 @@ foreach {net pin} [array get net2pin] {
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set_property HD.RECONFIGURABLE TRUE [get_cells roi]
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read_checkpoint -cell roi roi_inv.dcp
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read_checkpoint -cell roi inv_synth.dcp
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opt_design
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place_design
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route_design
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write_checkpoint -force roi_inv_w_harness_routed.dcp
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# Routed design of roi cell only
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write_checkpoint -force -cell roi roi_inv_routed.dcp
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# Replace roi cell with a black box and write the rest of the design
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update_design -cell roi -black_box
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lock_design -level routing
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write_checkpoint -force harness_routed.dcp
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write_checkpoint -force harness_impl.dcp
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@ -0,0 +1,3 @@
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read_verilog harness.v
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synth_design -top top -part $::env(XRAY_PART)
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write_checkpoint -force harness_synth.dcp
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@ -0,0 +1,53 @@
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//Connect the switches to the LEDs, inverting the signal in the ROI
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//Assumes # inputs = # outputs
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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wire [DIN_N-1:0] internal;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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//Very expensive inverter
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b10)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(internal[i]));
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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//Very expensive buffer
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b010)
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) lut (
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.I0(internal[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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@ -1,9 +0,0 @@
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//See README and tcl for more info
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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endmodule
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@ -0,0 +1,6 @@
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open_checkpoint harness_impl.dcp
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read_checkpoint -cell roi [lindex $argv 0]
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opt_design
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place_design
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route_design
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write_checkpoint -force [lindex $argv 1]
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@ -1,3 +0,0 @@
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read_verilog roi_inv.v
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synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
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write_checkpoint -force roi_inv.dcp
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@ -1,228 +0,0 @@
|
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INT_L_X10Y107.CENTER_INTER_L.SE6BEG0 NN6END0
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INT_L_X10Y104.CENTER_INTER_L.WL1BEG0 NW2END2
|
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INT_L_X10Y103.CENTER_INTER_L.EL1BEG0 NR1END1
|
||||
INT_L_X10Y103.CENTER_INTER_L.EL1BEG_N3 NW2END0
|
||||
INT_L_X10Y103.CENTER_INTER_L.FAN_ALT4 NR1END0
|
||||
INT_L_X10Y103.CENTER_INTER_L.NE2BEG3 NL1BEG_N3
|
||||
INT_L_X10Y103.CENTER_INTER_L.NL1BEG_N3 NL1END0
|
||||
INT_L_X10Y103.CENTER_INTER_L.SE2BEG2 EL1END2
|
||||
INT_L_X10Y103.CENTER_INTER_L.WW2BEG2 WL1END2
|
||||
CLBLM_L_X10Y102.SLICE_X13Y102.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y102.SLICE_X13Y102.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.BLUT.INIT[01] 1
|
||||
INT_L_X10Y102.CENTER_INTER_L.BYP_ALT5 NN2END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.EE2BEG2 NL1END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.EL1BEG_N3 NL1END0
|
||||
INT_L_X10Y102.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y102.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L12 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L14 NL1BEG_N3
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L15 FAN_BOUNCE_S3_4
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L17 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L18 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L24 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L27 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L6 WR1END3
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L7 BYP_BOUNCE5
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y102.CENTER_INTER_L.NL1BEG0 LOGIC_OUTS_L9
|
||||
INT_L_X10Y102.CENTER_INTER_L.NL1BEG_N3 LOGIC_OUTS_L8
|
||||
INT_L_X10Y102.CENTER_INTER_L.NR1BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y102.CENTER_INTER_L.NR1BEG1 LOGIC_OUTS_L13
|
||||
INT_L_X10Y102.CENTER_INTER_L.SE2BEG2 EL1END2
|
||||
INT_L_X10Y102.CENTER_INTER_L.SR1BEG2 WL1END1
|
||||
INT_L_X10Y102.CENTER_INTER_L.SW2BEG3 WL1END3
|
||||
INT_L_X10Y102.CENTER_INTER_L.WW2BEG2 WL1END2
|
||||
CLBLM_L_X10Y101.SLICE_X13Y101.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X13Y101.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X12Y101.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y101.SLICE_X12Y101.BLUT.INIT[01] 1
|
||||
INT_L_X10Y101.CENTER_INTER_L.BYP_ALT3 NL1BEG_N3
|
||||
INT_L_X10Y101.CENTER_INTER_L.BYP_ALT4 NW2END1
|
||||
INT_L_X10Y101.CENTER_INTER_L.ER1BEG2 LOGIC_OUTS_L13
|
||||
INT_L_X10Y101.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y101.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L12 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L14 SR1END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L15 BYP_BOUNCE3
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L17 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L18 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L24 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L27 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L6 BYP_BOUNCE4
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L7 NW2END_S0_0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y101.CENTER_INTER_L.LV_L18 SR1BEG_S0
|
||||
INT_L_X10Y101.CENTER_INTER_L.NE2BEG1 NR1END1
|
||||
INT_L_X10Y101.CENTER_INTER_L.NE2BEG3 NN6END3
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG0 LOGIC_OUTS_L9
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG2 WL1END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.NL1BEG_N3 LOGIC_OUTS_L8
|
||||
INT_L_X10Y101.CENTER_INTER_L.NN6BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y101.CENTER_INTER_L.SE2BEG2 EE2END2
|
||||
INT_L_X10Y101.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
CLBLM_L_X10Y100.SLICE_X13Y100.ALUT.INIT[01] 1
|
||||
CLBLM_L_X10Y100.SLICE_X13Y100.BLUT.INIT[01] 1
|
||||
CLBLM_L_X10Y100.SLICE_X12Y100.ALUT.INIT[01] 1
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT1 LOGIC_OUTS_L8
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT2 BYP_BOUNCE1
|
||||
INT_L_X10Y100.CENTER_INTER_L.BYP_ALT3 NL1BEG_N3
|
||||
INT_L_X10Y100.CENTER_INTER_L.EE2BEG3 NN6END3
|
||||
INT_L_X10Y100.CENTER_INTER_L.ER1BEG1 SR1BEG_S0
|
||||
INT_L_X10Y100.CENTER_INTER_L.GFAN0 GND_WIRE
|
||||
INT_L_X10Y100.CENTER_INTER_L.GFAN1 GND_WIRE
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L0 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L1 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L10 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L11 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L13 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L14 BYP_BOUNCE2
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L16 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L19 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L2 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L25 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L26 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L3 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L4 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L5 GFAN1
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L6 SW2END2
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L7 BYP_BOUNCE3
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L8 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.IMUX_L9 GFAN0
|
||||
INT_L_X10Y100.CENTER_INTER_L.NE2BEG0 LOGIC_OUTS_L12
|
||||
INT_L_X10Y100.CENTER_INTER_L.NE2BEG3 NE6END3
|
||||
INT_L_X10Y100.CENTER_INTER_L.NL1BEG_N3 WL1END_N1_3
|
||||
INT_L_X10Y100.CENTER_INTER_L.NN2BEG2 WL1END1
|
||||
INT_L_X10Y100.CENTER_INTER_L.NR1BEG1 LOGIC_OUTS_L9
|
||||
INT_L_X10Y100.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
INT_R_X11Y104.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y103.CENTER_INTER_R.NW2BEG2 NN2END2
|
||||
INT_R_X11Y103.CENTER_INTER_R.SL1BEG0 EL1END0
|
||||
INT_R_X11Y103.CENTER_INTER_R.WL1BEG2 SL1END3
|
||||
INT_R_X11Y103.CENTER_INTER_R.WL1BEG_N3 WR1END1
|
||||
CLBLM_R_X11Y102.SLICE_X14Y102.ALUT.INIT[01] 1
|
||||
CLBLM_R_X11Y102.SLICE_X14Y102.BLUT.INIT[01] 1
|
||||
INT_R_X11Y102.CENTER_INTER_R.EL1BEG0 LOGIC_OUTS13
|
||||
INT_R_X11Y102.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y102.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX12 GFAN1
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX15 EL1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX17 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX18 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX24 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX27 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX7 WR1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y102.CENTER_INTER_R.NW2BEG0 LOGIC_OUTS12
|
||||
INT_R_X11Y102.CENTER_INTER_R.SE2BEG1 NE2END1
|
||||
INT_R_X11Y102.CENTER_INTER_R.SL1BEG2 SE2END2
|
||||
INT_R_X11Y102.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG1 NW2END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG2 WL1END3
|
||||
INT_R_X11Y102.CENTER_INTER_R.WL1BEG_N3 SL1END0
|
||||
INT_R_X11Y102.CENTER_INTER_R.WR1BEG3 NR1END2
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.ALUT.INIT[01] 1
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.AMUX.O6 1
|
||||
CLBLM_R_X11Y101.SLICE_X14Y101.BLUT.INIT[01] 1
|
||||
INT_R_X11Y101.CENTER_INTER_R.EE2BEG2 ER1END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.EL1BEG0 LOGIC_OUTS13
|
||||
INT_R_X11Y101.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y101.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX12 GFAN1
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX15 EL1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX17 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX18 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX24 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX27 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX7 NR1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y101.CENTER_INTER_R.NN2BEG2 LOGIC_OUTS20
|
||||
INT_R_X11Y101.CENTER_INTER_R.NR1BEG2 SE2END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.NW2BEG0 NE2END0
|
||||
INT_R_X11Y101.CENTER_INTER_R.SL1BEG3 NE2END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.SR1BEG_S0 SL1END3
|
||||
INT_R_X11Y101.CENTER_INTER_R.SW2BEG2 SL1END2
|
||||
INT_R_X11Y101.CENTER_INTER_R.WL1BEG2 WR1END_S1_0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WL1BEG_N3 SR1BEG_S0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WW2BEG0 WL1END0
|
||||
INT_R_X11Y101.CENTER_INTER_R.WW2BEG1 WL1END1
|
||||
CLBLM_R_X11Y100.SLICE_X14Y100.ALUT.INIT[01] 1
|
||||
INT_R_X11Y100.CENTER_INTER_R.BYP_ALT5 ER1END1
|
||||
INT_R_X11Y100.CENTER_INTER_R.GFAN0 GND_WIRE
|
||||
INT_R_X11Y100.CENTER_INTER_R.GFAN1 GND_WIRE
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX1 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX11 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX2 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX4 GFAN1
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX7 BYP_BOUNCE5
|
||||
INT_R_X11Y100.CENTER_INTER_R.IMUX8 GFAN0
|
||||
INT_R_X11Y100.CENTER_INTER_R.NL1BEG_N3 LOGIC_OUTS12
|
||||
INT_R_X11Y100.CENTER_INTER_R.NR1BEG3 NL1BEG_N3
|
||||
INT_R_X11Y100.CENTER_INTER_R.NW2BEG1 WL1END0
|
||||
INT_R_X11Y100.CENTER_INTER_R.SR1BEG_S0 SL1END3
|
||||
INT_R_X11Y100.CENTER_INTER_R.WL1BEG1 SE2END2
|
||||
INT_R_X11Y100.CENTER_INTER_R.WL1BEG_N3 SR1BEG_S0
|
||||
INT_L_X12Y103.CENTER_INTER_L.WL1BEG_N3 SE6END0
|
||||
INT_L_X12Y103.CENTER_INTER_L.WR1BEG1 NR1END0
|
||||
INT_L_X12Y102.CENTER_INTER_L.NR1BEG0 EL1END0
|
||||
INT_L_X12Y102.CENTER_INTER_L.WR1BEG3 EE2END2
|
||||
INT_L_X12Y101.CENTER_INTER_L.NW2BEG3 NR1END3
|
||||
INT_L_X12Y101.CENTER_INTER_L.SE2BEG0 EL1END0
|
||||
INT_L_X12Y101.CENTER_INTER_L.WL1BEG0 SE2END1
|
||||
INT_L_X12Y101.CENTER_INTER_L.WL1BEG1 WR1END3
|
||||
INT_L_X12Y101.CENTER_INTER_L.WR1BEG_S0 NE6END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.EL1BEG2 NE6END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.LV_L18 WR1END0
|
||||
INT_L_X12Y100.CENTER_INTER_L.NR1BEG3 EE2END3
|
||||
INT_L_X12Y100.CENTER_INTER_L.SW6BEG3 LV_L18
|
||||
INT_L_X12Y100.CENTER_INTER_L.WL1BEG0 WR1END2
|
||||
INT_R_X13Y101.CENTER_INTER_R.WR1BEG3 EE2END2
|
||||
INT_R_X13Y100.CENTER_INTER_R.SL1BEG2 EL1END2
|
||||
INT_R_X13Y100.CENTER_INTER_R.WL1BEG_N3 SE2END0
|
||||
INT_R_X13Y100.CENTER_INTER_R.WR1BEG2 NR1END1
|
||||
INT_L_X16Y100.CENTER_INTER_L.ER1BEG1 SR1BEG_S0
|
||||
INT_L_X16Y100.CENTER_INTER_L.SR1BEG_S0 WL1END3
|
||||
INT_R_X17Y101.CENTER_INTER_R.WL1BEG_N3 WW2END0
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.DMUX.AX 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.ZINI 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.AFF.ZRST 1
|
||||
CLBLL_R_X17Y100.SLICE_X27Y100.FFSYNC 1
|
||||
INT_R_X17Y100.CENTER_INTER_R.BYP_ALT0 LOGIC_OUTS0
|
||||
INT_R_X17Y100.CENTER_INTER_R.CLK0 ER1END1
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
read_verilog [lindex $argv 0]
|
||||
synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
|
||||
write_checkpoint -force [lindex $argv 1]
|
||||
|
||||
Loading…
Reference in New Issue