From 40d3cb558891053a686297291ae4bf9d64728a99 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 25 Jul 2019 12:08:39 +0200 Subject: [PATCH] Added fuzzing of IDDR along with ISERDES Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/Makefile | 10 +- fuzzers/035b-iob-iserdes/generate.py | 60 +++++- fuzzers/035b-iob-iserdes/generate.tcl | 1 + fuzzers/035b-iob-iserdes/top.py | 270 +++++++++++++++++++------- 4 files changed, 256 insertions(+), 85 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index 1c3d2d23..ef4f5fb9 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,14 +1,14 @@ -N := 50 +N := 20 include ../fuzzer.mk database: build/segbits_xiob33.db -build/segbits_xiob33_msk.rdb: $(SPECIMENS_OK) - #${XRAY_SEGMATCH} -c -1 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) +build/segbits_xiob33.rdb: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) #python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE - python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt) + #python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt) -build/segbits_xiob33.db: build/segbits_xiob33_msk.rdb +build/segbits_xiob33.db: build/segbits_xiob33.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ ${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index b7343749..bd5978e0 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -30,7 +30,7 @@ for param_list in data: #loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) - # Serdes not used at all + # Site not used at all if not params["IS_USED"]: segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) @@ -62,15 +62,17 @@ for param_list in data: segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) - # Serdes used - else: + segmk.add_site_tag(loc, "IFF.IN_USE", 0) + + # Site used as ISERDESE2 + elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) @@ -170,6 +172,50 @@ for param_list in data: if value == "TRUE": segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) + # Site used as IDDR + elif verilog.unquote(params["BEL_TYPE"]) == "IDDR": + + segmk.add_site_tag(loc, "IFF.IN_USE", 1) + + if "DDR_CLK_EDGE" in params: + value = verilog.unquote(params["DDR_CLK_EDGE"]) + segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", int(value == "OPPOSITE_EDGE")) + segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", int(value == "SAME_EDGE")) + segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", int(value == "SAME_EDGE_PIPELINED")) + + if "SRTYPE" in params: + value = verilog.unquote(params["SRTYPE"]) + if value == "ASYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) + if value == "SYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) + + if "IDELMUX" in params: + if params["IDELMUX"] == 1: + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + else: + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + + if "IFFDELMUX" in params: + if params["IFFDELMUX"] == 1: + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + else: + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + + # Should not happen + else: + print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"])) + exit(-1) + # Write segments and tags for later check #with open("tags.json", "w") as fp: # tags = { diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index 1ee1c316..81985aa2 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -14,6 +14,7 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-98}] set_property IS_ENABLED 0 [get_drc_checks {REQP-109}] set_property IS_ENABLED 0 [get_drc_checks {REQP-111}] set_property IS_ENABLED 0 [get_drc_checks {REQP-103}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] place_design diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index d5472593..041268dc 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -42,10 +42,20 @@ def gen_sites(): iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0] iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0] - ilogic_s = iob33s.replace("IOB", "ILOGIC") - ilogic_m = iob33m.replace("IOB", "ILOGIC") - yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s + top_sites = { + "IOB": iob33m, + "ILOGIC": iob33m.replace("IOB", "ILOGIC"), + "IDELAY": iob33m.replace("IOB", "IDELAY"), + } + + bot_sites = { + "IOB": iob33s, + "ILOGIC": iob33s.replace("IOB", "ILOGIC"), + "IDELAY": iob33s.replace("IOB", "IDELAY"), + } + + yield iob_tile_name, top_sites, bot_sites def gen_iserdes(loc): @@ -55,6 +65,10 @@ def gen_iserdes(loc): verilog.quote(loc), "IS_USED": int(random.randint(0, 10) > 0), # Make it used more often + "USE_IDELAY": + random.randint(0, 1), + "BEL_TYPE": + verilog.quote("ISERDESE2"), "INIT_Q1": random.randint(0, 1), "INIT_Q2": @@ -124,6 +138,37 @@ def gen_iserdes(loc): return params +def gen_iddr(loc): + + # Site params + params = { + "SITE_LOC": + verilog.quote(loc), + "IS_USED": + int(random.randint(0, 10) > 0), # Make it used more often + "USE_IDELAY": + random.randint(0, 1), + "BEL_TYPE": + verilog.quote("IDDR"), + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "SRTYPE": + verilog.quote(random.choice(["ASYNC", "SYNC"])), + "DDR_CLK_EDGE": + verilog.quote(random.choice(["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])), + } + + if params["USE_IDELAY"]: + params["IDELMUX"] = random.randint(0, 1) + params["IFFDELMUX"] = random.randint(0, 1) + else: + params["IDELMUX"] = 0 + params["IFFDELMUX"] = 0 + + return params + def run(): # Get all [LR]IOI3 tiles @@ -145,6 +190,10 @@ module top ( wire [{N}:0] di_buf; wire [{N}:0] do_buf; + +// IDELAYCTRL +(* KEEP, DONT_TOUCH *) +IDELAYCTRL idelayctrl(); '''.format(**{"N": len(tiles) - 1})) # LOCes IOBs @@ -152,85 +201,100 @@ wire [{N}:0] do_buf; for i, sites in enumerate(tiles): tile_name = sites[0] - # Single ISERDES - if random.randint(0, 5) >= 1: +# # Single ISERDES +# if random.randint(0, 5) >= 1: - # Bottom site - if random.randint(0, 1): - iob_i = sites[1] - iob_o = sites[3] - ilogic = sites[2] - # Top site - else: - iob_i = sites[3] - iob_o = sites[1] - ilogic = sites[4] + # Top sites + if random.randint(0, 1): + this_sites = sites[1] + other_sites = sites[2] - # Generate cell - params = gen_iserdes(ilogic) - - # Instantiate the cell - print('') - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) - print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) - - params["CHAINED"] = 0 - - data.append([params]) - - # Dual ISERDES chained + # Bottom site else: + this_sites = sites[2] + other_sites = sites[1] - iob_i = sites[1] - iob_o = sites[3] - ilogic = [sites[2], sites[4]] - - # Generate cells - params_m = gen_iserdes(ilogic[0]) - params_s = gen_iserdes(ilogic[1]) + # Generate cell + bel_type = random.choice(["ISERDESE2", "IDDR"]) + if bel_type == "ISERDESE2": + params = gen_iserdes(this_sites["ILOGIC"]) + if bel_type == "IDDR": + params = gen_iddr(this_sites["ILOGIC"]) - # Force relevant parameters - params_m["SERDES_MODE"] = verilog.quote("MASTER") - params_m["IS_USED"] = 1 + params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"]) - params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") - params_m["DATA_RATE"] = verilog.quote("DDR") - params_m["DATA_WIDTH"] = random.choice([10, 14]) + # Instantiate the cell + print('') + print('// This : ' + " ".join(this_sites.values())) + print('// Other: ' + " ".join(other_sites.values())) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"]) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - params_s["SERDES_MODE"] = verilog.quote("SLAVE") - params_s["IS_USED"] = 1 + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + print('ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) - params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] - params_s["DATA_RATE"] = params_m["DATA_RATE"] - params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] + params["CHAINED"] = 0 - # Instantiate cells - print('') - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + # Params for the second site + other_params = { + "SITE_LOC": verilog.quote(other_sites["ILOGIC"]), + "IDELAY_LOC": verilog.quote(other_sites["IDELAY"]), + "IS_USED": 0, + } - print('wire o_%03d_m;' % i) - print('wire o_%03d_s;' % i) - print('wire [1:0] sh_%03d;' % i) - print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) - print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) - print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) + # Append to data list + data.append([params, other_params]) - params_m["SHIFTOUT_USED"] = 1 - - params_m["CHAINED"] = 1 - params_s["CHAINED"] = 1 - - data.append([params_m, params_s]) +# # Dual ISERDES chained +# else: +# +# iob_i = sites[1] +# iob_o = sites[3] +# ilogic = [sites[2], sites[4]] +# +# # Generate cells +# params_m = gen_iserdes(ilogic[0]) +# params_s = gen_iserdes(ilogic[1]) +# +# # Force relevant parameters +# params_m["SERDES_MODE"] = verilog.quote("MASTER") +# params_m["IS_USED"] = 1 +# +# params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") +# params_m["DATA_RATE"] = verilog.quote("DDR") +# params_m["DATA_WIDTH"] = random.choice([10, 14]) +# +# params_s["SERDES_MODE"] = verilog.quote("SLAVE") +# params_s["IS_USED"] = 1 +# +# params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] +# params_s["DATA_RATE"] = params_m["DATA_RATE"] +# params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] +# +# # Instantiate cells +# print('') +# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) +# print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) +# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) +# print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) +# +# print('wire o_%03d_m;' % i) +# print('wire o_%03d_s;' % i) +# print('wire [1:0] sh_%03d;' % i) +# print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) +# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) +# print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) +# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) +# print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) +# +# params_m["SHIFTOUT_USED"] = 1 +# +# params_m["CHAINED"] = 1 +# params_s["CHAINED"] = 1 +# +# data.append([params_m, params_s]) # Store params with open("params.json", "w") as fp: @@ -241,7 +305,7 @@ wire [{N}:0] do_buf; endmodule (* KEEP, DONT_TOUCH *) -module iserdes_single( +module ilogic_single( input wire clk1, input wire clk2, input wire I, @@ -252,6 +316,11 @@ module iserdes_single( parameter SITE_LOC = ""; parameter IS_USED = 1; +parameter BEL_TYPE = "ISERDESE2"; +parameter IDELAY_LOC = ""; +parameter USE_IDELAY = 0; +parameter IDELMUX = 0; +parameter IFFDELMUX = 0; parameter INTERFACE_TYPE = "NETWORKING"; parameter DATA_RATE = "DDR"; parameter DATA_WIDTH = 4; @@ -276,11 +345,41 @@ parameter DYN_CLKDIV_INV_EN = "FALSE"; parameter DYN_CLK_INV_EN = "FALSE"; parameter IOBDELAY = "NONE"; parameter OFB_USED = "FALSE"; +parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; +parameter SRTYPE = "ASYNC"; wire [7:0] x; +wire ddly; (* KEEP, DONT_TOUCH *) -generate if (IS_USED) begin +generate if (IS_USED && USE_IDELAY) begin + + // IDELAY + (* LOC=IDELAY_LOC, KEEP, DONT_TOUCH *) + IDELAYE2 idelay + ( + .C(clk), + .REGRST(), + .LD(), + .CE(), + .INC(), + .CINVCTRL(), + .CNTVALUEIN(), + .IDATAIN(I), + .DATAIN(), + .LDPIPEEN(), + .DATAOUT(ddly), + .CNTVALUEOUT() + ); + +end else begin + + assign ddly = 0; + +end endgenerate + +(* KEEP, DONT_TOUCH *) +generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin // ISERDES (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) @@ -343,6 +442,31 @@ generate if (IS_USED) begin .SHIFTOUT2(shiftout[1]) ); +end else if (IS_USED && BEL_TYPE == "IDDR") begin + + // IDDR + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) + IDDR # + ( + .DDR_CLK_EDGE(DDR_CLK_EDGE), + .INIT_Q1(INIT_Q1), + .INIT_Q2(INIT_Q2), + .SRTYPE(SRTYPE) + ) + iddr + ( + .C(clk1), + .CE(), + .D( (IFFDELMUX) ? ddly : I ), + .S(), + .R(), + .Q1(x[0]), + .Q2(x[1]) + ); + + assign x[2] = (IDELMUX) ? ddly : I; + assign x[7:3] = 0; + end else begin assign x[0] = I;