mirror of https://github.com/openXC7/prjxray.git
Update / clean up ffconfig using experiment. push db
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
80fcae8c57
commit
3b303b38ed
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@ -1,8 +0,0 @@
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/specimen_*
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@ -1,22 +0,0 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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@ -1,120 +0,0 @@
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#!/usr/bin/env python3
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'''
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FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
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FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
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FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
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FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set
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LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
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LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
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'''
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from prims import *
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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def ones(l):
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#return l + [x + '_1' for x in l]
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#return sorted(l + [x + '_1' for x in l])
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ret = []
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for x in l:
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ret.append(x)
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ret.append(x + '_1')
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return ret
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def loadtop():
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'''
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i,prim,loc,bel
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0,FDPE,SLICE_X12Y100,C5FF
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1,FDPE,SLICE_X15Y100,A5FF
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2,FDPE_1,SLICE_X16Y100,B5FF
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3,LDCE_1,SLICE_X17Y100,BFF
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'''
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f = open('top.txt', 'r')
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f.readline()
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ret = {}
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for l in f:
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i,prim,loc,bel,init = l.split(",")
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i = int(i)
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init = int(init)
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ret[loc] = (i,prim,loc,bel,init)
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return ret
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top = loadtop()
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def vs2i(s):
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return {"1'b0": 0, "1'b1": 1}[s]
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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for line in f:
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'''
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
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'''
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line = line.split()
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tile_type = line[0]
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tile_name = line[1]
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grid_x = line[2]
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grid_y = line[3]
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# Other code uses BEL name
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# SLICE_X12Y137/D5FF
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site_ff_name = line[4]
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site, ff_name = site_ff_name.split('/')
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ff_type = line[5]
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used = int(line[6])
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cel_prim = None
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cel_name = None
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if used:
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cel_name = line[7]
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# ex: FDCE
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cel_prim = line[8]
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# 1'b1
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# cinv = int(line[9][-1])
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cinv = int(line[9])
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init = vs2i(line[10])
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#init = int(line[10])
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# A B C D
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which = ff_name[0]
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# LUT6 vs LUT5 FF
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is5 = '5' in ff_name
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if used:
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segmk.addtag(site, "%s.ZINIT" % ff_name, 1 ^ init)
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# CLKINV turns out to be more complicated than origianlly thought
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if isff(cel_prim):
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segmk.addtag(site, "CLKINV", cinv)
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else:
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segmk.addtag(site, "CLKINV", 1 ^ cinv)
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# Synchronous vs asynchronous FF
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# Unlike most bits, shared between all CLB FFs
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segmk.addtag(site, "FFSYNC",
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cel_prim in ('FDSE', 'FDRE'))
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# Latch bit
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# Only applies to LUT6 (non-5) FF's
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if not is5:
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segmk.addtag(site, "LATCH", isl(cel_prim))
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'''
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On name:
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The primitives you listed have a control input to set the FF value to zero (clear/reset),
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the other three primitives have a control input that sets the FF value to one.
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Z => inversion
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'''
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segmk.addtag(site, "%s.ZRESET" % ff_name,
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cel_prim in ('FDRE', 'FDCE', 'LDCE'))
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segmk.compile()
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segmk.write()
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@ -1,17 +0,0 @@
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#!/bin/bash
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set -ex
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. ../../utils/genheader.sh
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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@ -1,64 +0,0 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# Get all FF's in pblock
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set ffs [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ *} */*FF]
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set fp [open "design.txt" w]
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# set ff [lindex $ffs 0]
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# set ff [get_bels SLICE_X23Y100/AFF]
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# proc putl {lst} { foreach line $lst {puts $line} }
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foreach ff $ffs {
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set tile [get_tile -of_objects $ff]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set type [get_property TYPE $tile]
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set bel_type [get_property TYPE $ff]
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set used [get_property IS_USED $ff]
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set usedstr ""
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if $used {
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set ffc [get_cells -of_objects $ff]
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set cell_bel [get_property BEL $ffc]
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# ex: FDRE
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set ref_name [get_property REF_NAME $ffc]
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#set cinv [get_property IS_C_INVERTED $ffc]
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# FF have clock pin
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# Latches have gate pin
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set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
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set cinv [get_property IS_INVERTED $cpin]
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set init [get_property INIT $ffc]
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set usedstr "$cell_bel $ref_name $cinv $init"
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}
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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}
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close $fp
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@ -1,2 +1,10 @@
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/specimen_[0-9][0-9][0-9]/
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/seg_clblx.segbits
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/specimen_*
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/__pycache__/
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/*.segbits
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@ -1,10 +1,9 @@
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N := 3
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr]_[0-9].txt,$(SPECIMENS))
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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@ -17,7 +16,7 @@ $(SPECIMENS_OK):
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clbll.segbits seg_clblm.segbits
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb regen clean
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.PHONY: database pushdb clean
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@ -1,38 +1,120 @@
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#!/usr/bin/env python3
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'''
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FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
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FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
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FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
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FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set
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LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
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LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
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'''
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from prims import *
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design_%s.bits" % sys.argv[1])
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segmk = segmaker("design.bits")
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print("Loading tags from design_%s.txt." % sys.argv[1])
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with open("design_%s.txt" % sys.argv[1], "r") as f:
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def ones(l):
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#return l + [x + '_1' for x in l]
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#return sorted(l + [x + '_1' for x in l])
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ret = []
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for x in l:
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ret.append(x)
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ret.append(x + '_1')
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return ret
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def loadtop():
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'''
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i,prim,loc,bel
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0,FDPE,SLICE_X12Y100,C5FF
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1,FDPE,SLICE_X15Y100,A5FF
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2,FDPE_1,SLICE_X16Y100,B5FF
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3,LDCE_1,SLICE_X17Y100,BFF
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'''
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f = open('top.txt', 'r')
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f.readline()
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ret = {}
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for l in f:
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i,prim,loc,bel,init = l.split(",")
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i = int(i)
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init = int(init)
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ret[loc] = (i,prim,loc,bel,init)
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return ret
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top = loadtop()
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def vs2i(s):
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return {"1'b0": 0, "1'b1": 1}[s]
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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for line in f:
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'''
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
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CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
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'''
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line = line.split()
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site = line[0]
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bel = line[1]
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ctype = line[2]
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init = int(line[3][3])
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cinv = int(line[4][3])
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tile_type = line[0]
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tile_name = line[1]
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grid_x = line[2]
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grid_y = line[3]
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# Other code uses BEL name
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# SLICE_X12Y137/D5FF
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site_ff_name = line[4]
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site, ff_name = site_ff_name.split('/')
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ff_type = line[5]
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used = int(line[6])
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cel_prim = None
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cel_name = None
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if used:
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cel_name = line[7]
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# ex: FDCE
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cel_prim = line[8]
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# 1'b1
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# cinv = int(line[9][-1])
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cinv = int(line[9])
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init = vs2i(line[10])
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#init = int(line[10])
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if False:
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segmk.addtag(site, "%s.TYPE_%s" % (bel, ctype), 1)
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# A B C D
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which = ff_name[0]
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# LUT6 vs LUT5 FF
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is5 = '5' in ff_name
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for i in range(1, 15):
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types = set()
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if i & 1: types.add("FDCE")
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if i & 2: types.add("FDPE")
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if i & 4: types.add("FDRE")
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if i & 8: types.add("FDSE")
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segmk.addtag(site, "%s.TYPES_%s" % (bel, "_".join(sorted(types))), ctype in types)
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if used:
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segmk.addtag(site, "%s.ZINIT" % ff_name, 1 ^ init)
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if False:
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segmk.addtag(site, "%s.CLOCK_INV" % (bel.split(".")[0]), cinv)
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# CLKINV turns out to be more complicated than origianlly thought
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if isff(cel_prim):
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segmk.addtag(site, "CLKINV", cinv)
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else:
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segmk.addtag(site, "CLKINV", 1 ^ cinv)
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segmk.addtag(site, "%s.ZINI" % bel, 1-init)
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# Synchronous vs asynchronous FF
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# Unlike most bits, shared between all CLB FFs
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segmk.addtag(site, "FFSYNC",
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cel_prim in ('FDSE', 'FDRE'))
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# Latch bit
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# Only applies to LUT6 (non-5) FF's
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if not is5:
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segmk.addtag(site, "LATCH", isl(cel_prim))
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'''
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On name:
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The primitives you listed have a control input to set the FF value to zero (clear/reset),
|
||||
the other three primitives have a control input that sets the FF value to one.
|
||||
Z => inversion
|
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'''
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segmk.addtag(site, "%s.ZRESET" % ff_name,
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cel_prim in ('FDRE', 'FDCE', 'LDCE'))
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segmk.compile()
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segmk.write(sys.argv[1])
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segmk.write()
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|
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@ -1,16 +1,17 @@
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#!/bin/bash
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source ${XRAY_GENHEADER}
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set -ex
|
||||
|
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echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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. ../../utils/genheader.sh
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|
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
|
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|
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python3 ../top.py >top.v
|
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vivado -mode batch -source ../generate.tcl
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|
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for i in {0..9}; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_$i.bits -z -y design_$i.bit
|
||||
for x in design*.bit; do
|
||||
../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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||||
done
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|
||||
for i in {0..9}; do
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python3 ../generate.py $i
|
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done
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python3 ../generate.py
|
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|
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|
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|
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@ -1,14 +1,14 @@
|
|||
create_project -force -part $::env(XRAY_PART) design design
|
||||
|
||||
read_verilog ../top.v
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports rst]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
|
||||
|
||||
create_pblock roi
|
||||
set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
|
||||
|
||||
|
|
@ -22,43 +22,43 @@ place_design
|
|||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
||||
########################################
|
||||
# Unmodified design with random LUTs
|
||||
|
||||
proc write_txtdata {filename} {
|
||||
puts "Writing $filename."
|
||||
set fp [open $filename w]
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE || REF_NAME == FDSE || REF_NAME == FDCE || REF_NAME == FDPE}] {
|
||||
set loc [get_property LOC $cell]
|
||||
set bel [get_property BEL $cell]
|
||||
set ctype [get_property REF_NAME $cell]
|
||||
set init [get_property INIT $cell]
|
||||
set cinv [get_property IS_C_INVERTED $cell]
|
||||
puts $fp "$loc $bel $ctype $init $cinv"
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
write_bitstream -force design_0.bit
|
||||
write_txtdata design_0.txt
|
||||
|
||||
|
||||
########################################
|
||||
# Versions with random config changes
|
||||
|
||||
proc change_design_randomly {} {
|
||||
foreach cell [get_cells -hierarchical -filter {REF_NAME == FDRE}] {
|
||||
set site_cells [get_cells -of_objects [get_sites -of_objects $cell] -filter {REF_NAME == FDRE || REF_NAME == FDSE || REF_NAME == FDCE || REF_NAME == FDPE}]
|
||||
set_property INIT 1'b[expr int(rand()*2)] $cell
|
||||
set_property IS_C_INVERTED 1'b[expr int(rand()*2)] $site_cells
|
||||
}
|
||||
}
|
||||
|
||||
for {set i 1} {$i < 10} {incr i} {
|
||||
change_design_randomly
|
||||
write_bitstream -force design_$i.bit
|
||||
write_txtdata design_$i.txt
|
||||
# Get all FF's in pblock
|
||||
set ffs [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ *} */*FF]
|
||||
|
||||
set fp [open "design.txt" w]
|
||||
# set ff [lindex $ffs 0]
|
||||
# set ff [get_bels SLICE_X23Y100/AFF]
|
||||
# proc putl {lst} { foreach line $lst {puts $line} }
|
||||
foreach ff $ffs {
|
||||
set tile [get_tile -of_objects $ff]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
set type [get_property TYPE $tile]
|
||||
set bel_type [get_property TYPE $ff]
|
||||
set used [get_property IS_USED $ff]
|
||||
set usedstr ""
|
||||
|
||||
if $used {
|
||||
set ffc [get_cells -of_objects $ff]
|
||||
set cell_bel [get_property BEL $ffc]
|
||||
# ex: FDRE
|
||||
set ref_name [get_property REF_NAME $ffc]
|
||||
#set cinv [get_property IS_C_INVERTED $ffc]
|
||||
|
||||
# FF have clock pin
|
||||
# Latches have gate pin
|
||||
set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
|
||||
set cinv [get_property IS_INVERTED $cpin]
|
||||
|
||||
set init [get_property INIT $ffc]
|
||||
|
||||
set usedstr "$cell_bel $ref_name $cinv $init"
|
||||
}
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
|
|||
|
|
@ -1,83 +0,0 @@
|
|||
`include "setseed.vh"
|
||||
|
||||
module top(input clk, rst, di, output do);
|
||||
roi roi (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.din(di),
|
||||
.dout(do)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module roi(input clk, input rst, input din, output dout);
|
||||
localparam integer N = 500;
|
||||
|
||||
wire [N:0] nets;
|
||||
|
||||
assign nets[0] = din;
|
||||
assign dout = nets[N];
|
||||
|
||||
function [31:0] xorshift32(input [31:0] v);
|
||||
begin
|
||||
xorshift32 = v;
|
||||
xorshift32 = xorshift32 ^ (xorshift32 << 13);
|
||||
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
|
||||
xorshift32 = xorshift32 ^ (xorshift32 << 5);
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [31:0] hash32(input [31:0] v);
|
||||
begin
|
||||
hash32 = v ^ `SEED;
|
||||
hash32 = xorshift32(hash32);
|
||||
hash32 = xorshift32(hash32);
|
||||
hash32 = xorshift32(hash32);
|
||||
hash32 = xorshift32(hash32);
|
||||
end
|
||||
endfunction
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < N; i = i+1) begin:ffs
|
||||
localparam integer fftype = hash32(i) % 4;
|
||||
case (fftype)
|
||||
0: begin
|
||||
FDRE ff (
|
||||
.C(clk),
|
||||
.D(nets[i]),
|
||||
.Q(nets[i+1]),
|
||||
.R(rst),
|
||||
.CE(1'b1)
|
||||
);
|
||||
end
|
||||
1: begin
|
||||
FDSE ff (
|
||||
.C(clk),
|
||||
.D(nets[i]),
|
||||
.Q(nets[i+1]),
|
||||
.S(rst),
|
||||
.CE(1'b1)
|
||||
);
|
||||
end
|
||||
2: begin
|
||||
FDCE ff (
|
||||
.C(clk),
|
||||
.D(nets[i]),
|
||||
.Q(nets[i+1]),
|
||||
.CLR(rst),
|
||||
.CE(1'b1)
|
||||
);
|
||||
end
|
||||
3: begin
|
||||
FDPE ff (
|
||||
.C(clk),
|
||||
.D(nets[i]),
|
||||
.Q(nets[i+1]),
|
||||
.PRE(rst),
|
||||
.CE(1'b1)
|
||||
);
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/.Xil
|
||||
/design/
|
||||
/design.bit
|
||||
/design.bits
|
||||
/design.dcp
|
||||
/usage_statistics_webtalk.*
|
||||
/vivado*
|
||||
/specimen_*
|
||||
/*.segbits
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
N := 1
|
||||
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
|
||||
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
|
||||
|
||||
database: $(SPECIMENS_OK)
|
||||
${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
|
||||
|
||||
pushdb:
|
||||
${XRAY_MERGEDB} clbll_l seg_clblx.segbits
|
||||
${XRAY_MERGEDB} clbll_r seg_clblx.segbits
|
||||
${XRAY_MERGEDB} clblm_l seg_clblx.segbits
|
||||
${XRAY_MERGEDB} clblm_r seg_clblx.segbits
|
||||
|
||||
$(SPECIMENS_OK):
|
||||
bash generate.sh $(subst /OK,,$@)
|
||||
touch $@
|
||||
|
||||
clean:
|
||||
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
|
||||
|
||||
.PHONY: database pushdb clean
|
||||
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
Clock inversion is per slice (as BEL CLKINV)
|
||||
Vivado GUI is misleading as it often shows it per FF, which is not actually true
|
||||
0: normal clock
|
||||
1: invert clock
|
||||
CLB.SLICE_X0.CLKINV 01_51
|
||||
CLB.SLICE_X1.CLKINV 00_52
|
||||
|
||||
Note: Vivado uses inverted clock macros with "_1" to infer this mux
|
||||
Ex: FDCE_1 is inverted, FDCE is normal
|
||||
It is illegal to place both in the same slice
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import sys, re
|
||||
|
||||
sys.path.append("../../../utils/")
|
||||
from segmaker import segmaker
|
||||
|
||||
segmk = segmaker("design.bits")
|
||||
|
||||
ffprims = (
|
||||
'FD',
|
||||
'FD_1',
|
||||
'FDC',
|
||||
'FDC_1',
|
||||
'FDCE',
|
||||
'FDCE_1',
|
||||
'FDE',
|
||||
'FDE_1',
|
||||
'FDP',
|
||||
'FDP_1',
|
||||
'FDPE',
|
||||
'FDPE_1',
|
||||
'FDR',
|
||||
'FDR_1',
|
||||
'FDRE',
|
||||
'FDRE_1',
|
||||
'FDS',
|
||||
'FDS_1',
|
||||
'FDSE',
|
||||
'FDSE_1',
|
||||
)
|
||||
ffprims = (
|
||||
'FDRE',
|
||||
'FDSE',
|
||||
'FDCE',
|
||||
'FDPE',
|
||||
)
|
||||
|
||||
print("Loading tags from design.txt")
|
||||
with open("design.txt", "r") as f:
|
||||
for line in f:
|
||||
'''
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
|
||||
CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
|
||||
CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
|
||||
'''
|
||||
line = line.split()
|
||||
tile_type = line[0]
|
||||
tile_name = line[1]
|
||||
grid_x = line[2]
|
||||
grid_y = line[3]
|
||||
# Other code uses BEL name
|
||||
site_ff_name = line[4]
|
||||
site, ff_name = site_ff_name.split('/')
|
||||
ff_type = line[5]
|
||||
used = int(line[6])
|
||||
ref_name = None
|
||||
cel_name = None
|
||||
if used:
|
||||
_cel_name = line[7]
|
||||
_ref_name = line[8]
|
||||
# 1'b1
|
||||
# cinv = int(line[9][-1])
|
||||
cinv = int(line[9])
|
||||
|
||||
which = ff_name[0]
|
||||
# We only need one FF...we think
|
||||
#if ff_name != 'AFF':
|
||||
# continue
|
||||
|
||||
# Compare '_1' negative edge clock to positive edge
|
||||
if used:
|
||||
inv_clk = cinv
|
||||
segmk.addtag(site, "CLKINV", inv_clk)
|
||||
|
||||
segmk.compile()
|
||||
segmk.write()
|
||||
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -ex
|
||||
|
||||
. ../../utils/genheader.sh
|
||||
|
||||
#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
|
||||
|
||||
python3 ../top.py >top.v
|
||||
vivado -mode batch -source ../generate.tcl
|
||||
|
||||
for x in design*.bit; do
|
||||
../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
|
||||
done
|
||||
|
||||
python3 ../generate.py
|
||||
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
|
||||
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
|
||||
|
||||
create_pblock roi
|
||||
set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
|
||||
|
||||
|
||||
# Get all FF's in pblock
|
||||
set ffs [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ *} */*FF]
|
||||
|
||||
set fp [open "design.txt" w]
|
||||
# set ff [lindex $ffs 0]
|
||||
# set ff [get_bels SLICE_X23Y100/AFF]
|
||||
# proc putl {lst} { foreach line $lst {puts $line} }
|
||||
foreach ff $ffs {
|
||||
set tile [get_tile -of_objects $ff]
|
||||
set grid_x [get_property GRID_POINT_X $tile]
|
||||
set grid_y [get_property GRID_POINT_Y $tile]
|
||||
set type [get_property TYPE $tile]
|
||||
set bel_type [get_property TYPE $ff]
|
||||
set used [get_property IS_USED $ff]
|
||||
set usedstr ""
|
||||
if $used {
|
||||
set ffc [get_cells -of_objects $ff]
|
||||
set cell_bel [get_property BEL $ffc]
|
||||
# ex: FDRE
|
||||
set ref_name [get_property REF_NAME $ffc]
|
||||
#set cinv [get_property IS_C_INVERTED $ffc]
|
||||
|
||||
set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C}]
|
||||
set cinv [get_property IS_INVERTED $cpin]
|
||||
set usedstr "$cell_bel $ref_name $cinv"
|
||||
}
|
||||
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
|
||||
}
|
||||
close $fp
|
||||
|
||||
|
|
@ -1,357 +0,0 @@
|
|||
import random
|
||||
import os
|
||||
|
||||
random.seed(0)
|
||||
|
||||
CLBN = 600
|
||||
|
||||
# TODO: get this from the environment var
|
||||
assert os.getenv('XRAY_ROI') == 'SLICE_X12Y100:SLICE_X27Y149'
|
||||
# SLICE_X12Y100
|
||||
# SLICE_X27Y149
|
||||
SLICEX = (12, 28)
|
||||
SLICEY = (100, 150)
|
||||
|
||||
# 800
|
||||
SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
|
||||
print('//SLICEX: %s' % str(SLICEX))
|
||||
print('//SLICEY: %s' % str(SLICEY))
|
||||
print('//SLICEN: %s' % str(SLICEN))
|
||||
print('//Requested CLBs: %s' % str(CLBN))
|
||||
|
||||
def gen_slices():
|
||||
for slicey in range(*SLICEY):
|
||||
for slicex in range(*SLICEX):
|
||||
yield "SLICE_X%dY%d" % (slicex, slicey)
|
||||
|
||||
DIN_N = CLBN * 4
|
||||
DOUT_N = CLBN * 1
|
||||
ffprims = (
|
||||
'FD',
|
||||
'FD_1',
|
||||
'FDC',
|
||||
'FDC_1',
|
||||
'FDCE',
|
||||
'FDCE_1',
|
||||
'FDE',
|
||||
'FDE_1',
|
||||
'FDP',
|
||||
'FDP_1',
|
||||
'FDPE',
|
||||
'FDPE_1',
|
||||
'FDR',
|
||||
'FDR_1',
|
||||
'FDRE',
|
||||
'FDRE_1',
|
||||
'FDS',
|
||||
'FDS_1',
|
||||
'FDSE',
|
||||
'FDSE_1',
|
||||
)
|
||||
ff_bels = (
|
||||
'AFF',
|
||||
'A5FF',
|
||||
'BFF',
|
||||
'B5FF',
|
||||
'CFF',
|
||||
'C5FF',
|
||||
'DFF',
|
||||
'D5FF',
|
||||
)
|
||||
|
||||
print('''
|
||||
module top(input clk, stb, di, output do);
|
||||
localparam integer DIN_N = %d;
|
||||
localparam integer DOUT_N = %d;
|
||||
|
||||
reg [DIN_N-1:0] din;
|
||||
wire [DOUT_N-1:0] dout;
|
||||
|
||||
reg [DIN_N-1:0] din_shr;
|
||||
reg [DOUT_N-1:0] dout_shr;
|
||||
|
||||
always @(posedge clk) begin
|
||||
din_shr <= {din_shr, di};
|
||||
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
|
||||
if (stb) begin
|
||||
din <= din_shr;
|
||||
dout_shr <= dout;
|
||||
end
|
||||
end
|
||||
|
||||
assign do = dout_shr[DOUT_N-1];
|
||||
|
||||
roi roi (
|
||||
.clk(clk),
|
||||
.din(din),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
''' % (DIN_N, DOUT_N))
|
||||
|
||||
slices = gen_slices()
|
||||
print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
|
||||
for i in range(CLBN):
|
||||
ffprim = random.choice(ffprims)
|
||||
# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
|
||||
# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
|
||||
loc = next(slices)
|
||||
bel = random.choice(ff_bels)
|
||||
#bel = "AFF"
|
||||
print(' clb_%s' % ffprim)
|
||||
print(' #(.LOC("%s"), .BEL("%s"))' % (loc, bel))
|
||||
print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i))
|
||||
print('''endmodule
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
''')
|
||||
|
||||
print('''
|
||||
module clb_FD (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y100";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FD ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FD_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y101";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FD_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDC (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y102";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDC ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CLR(din[0]),
|
||||
.D(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDC_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y103";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDC_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CLR(din[0]),
|
||||
.D(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDCE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y104";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDCE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.CLR(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDCE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y105";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDCE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.CLR(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y106";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.CE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y107";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.CE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDP (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y108";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDP ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.PRE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDP_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y109";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDP_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.PRE(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDPE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y110";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDPE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.PRE(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDPE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y111";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDPE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.PRE(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDR (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y112";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDR ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.R(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDR_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y113";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDR_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.D(din[0]),
|
||||
.R(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDRE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y114";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDRE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.R(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDRE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y115";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDRE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.R(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDS (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y116";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDS ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.S(din[0]),
|
||||
.D(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDS_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y117";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDS_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.S(din[0]),
|
||||
.D(din[1])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDSE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y118";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDSE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.S(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
|
||||
module clb_FDSE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y119";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
FDSE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
.CE(din[0]),
|
||||
.S(din[1]),
|
||||
.D(din[2])
|
||||
);
|
||||
endmodule
|
||||
''')
|
||||
|
||||
Loading…
Reference in New Issue