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fixedpnr: fix latch INV/INIT polarity 

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster 2017-11-28 16:25:39 -08:00 committed by Tim 'mithro' Ansell
parent ee3613e047
commit 80fcae8c57
3 changed files with 18 additions and 3 deletions
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15
minitests/fixedpnr/runme.sh
View File

@ -7,4 +7,17 @@ for ff in fdre fdse fdce fdce_inv fdpe ldce ldpe; do
${XRAY_SEGPRINT} -z design_$ff.bits >design_$ff.seg
done
diff -u design_fdre.bits design_fdse.bits
# Clock inverter bit
diff design_fdce.seg design_fdce_inv.seg || true
# Bits set on FF's are a superset of FDPE
# FDSE has the most bits set
diff design_fdpe.seg design_fdse.seg || true
diff design_fdpe.seg design_fdce.seg || true
diff design_fdpe.seg design_fdre.seg || true
# the latch bit
diff design_fdpe.seg design_ldpe.seg || true
# LDPE has one more bit pair set than LDCE
# This is the same pair FDRE/LDCE have
diff design_ldpe.seg design_ldce.seg || true

3
minitests/fixedpnr/top_ldce.v
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@ -1,7 +1,8 @@
module top(input clk, ce, sr, d, output q);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
LDCE ff (
//Keep inverter off
LDCE_1 ff (
.G(clk),
.GE(ce),
.CLR(sr),

3
minitests/fixedpnr/top_ldpe.v
View File

@ -1,7 +1,8 @@
module top(input clk, ce, sr, d, output q);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
LDPE ff (
//Keep inverter off
LDPE_1 ff (
.G(clk),
.GE(ce),
.PRE(sr),