tilegrid pll: basic support

Signed-off-by: John McMaster <johndmcmaster@gmail.com>

fuzzers/005-tilegrid/Makefile

@@ -22,7 +22,7 @@ build/bram/deltas:
 build/iob/deltas:
 	bash generate.sh build/iob iob
 
-build/tilegrid_tdb.json: iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb
+build/tilegrid_tdb.json: iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
 	python3 add_tdb.py --fn-in build/basicdb/tilegrid.json --fn-out build/tilegrid_tdb.json
 
 iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
@@ -31,6 +31,9 @@ iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 mmcm/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd mmcm && $(MAKE)
 
+pll/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
+	cd pll && $(MAKE)
+
 build/tilegrid.json: generate_full.py build/tilegrid_tdb.json build/clb/deltas build/bram/deltas
 	cd build && python3 ${FUZDIR}/generate_full.py \
         --json-in tilegrid_tdb.json --json-out ${BUILD_DIR}/tilegrid.json \
@@ -46,6 +49,7 @@ clean:
 	rm -rf build
 	cd iob && $(MAKE) clean
 	cd mmcm && $(MAKE) clean
+	cd pll && $(MAKE) clean
 
 .PHONY: database pushdb clean run
 

fuzzers/005-tilegrid/add_tdb.py

@@ -98,6 +98,8 @@ def run(fn_in, fn_out, verbose=False):
         ("iob/build/segbits_tilegrid.tdb", 42, 4),
         # FIXME: height
         ("mmcm/build/segbits_tilegrid.tdb", 30, 4),
+        # FIXME: height
+        ("pll/build/segbits_tilegrid.tdb", 30, 4),
     ]
     for (tdb_fn, frames, words) in tdb_fns:
         for (tile, frame, wordidx) in load_db(tdb_fn):

fuzzers/005-tilegrid/mmcm/Makefile

@@ -1,4 +1,5 @@
 N ?= 2
 # Was expecting oneval 3, but bits might be inverted
+# FIXME: dword
 GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1D --dword 0 --dbit 15"
 include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/pll/Makefile

@@ -0,0 +1,5 @@
+N ?= 2
+# Was expecting oneval 3, but bits might be inverted
+# FIXME: dword
+GENERATE_ARGS?="--oneval 2 --design params.csv --dframe 1C --dword 0 --dbit 16"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/pll/generate.tcl

@@ -0,0 +1,35 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+    # Disable MMCM frequency etc sanity checks
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+    # PLL
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
+
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/pll/top.py

@@ -0,0 +1,90 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+
+
+def gen_sites():
+    for tile_name, site_name, _site_type in util.get_roi().gen_sites(
+        ['PLLE2_ADV']):
+        yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print(
+        '''
+module top(input clk, stb, di, output do);
+    localparam integer DIN_N = 8;
+    localparam integer DOUT_N = 8;
+
+    reg [DIN_N-1:0] din;
+    wire [DOUT_N-1:0] dout;
+
+    reg [DIN_N-1:0] din_shr;
+    reg [DOUT_N-1:0] dout_shr;
+
+    always @(posedge clk) begin
+        din_shr <= {din_shr, di};
+        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+        if (stb) begin
+            din <= din_shr;
+            dout_shr <= dout;
+        end
+    end
+
+    assign do = dout_shr[DOUT_N-1];
+    ''')
+
+    params = {}
+    # FIXME: can't LOC?
+    # only one for now, worry about later
+    sites = list(gen_sites())
+    assert len(sites) == 1
+    for (tile_name, site_name), isone in zip(sites,
+                                             util.gen_fuzz_states(len(sites))):
+        # 0 is invalid
+        # shift one bit, keeping LSB constant
+        CLKOUT1_DIVIDE = {0: 2, 1: 3}[isone]
+        params[tile_name] = (site_name, CLKOUT1_DIVIDE)
+
+        print(
+            '''
+    (* KEEP, DONT_TOUCH *)
+    PLLE2_ADV #(/*.LOC("%s"),*/ .CLKOUT1_DIVIDE(%u)) dut_%s(
+            .CLKFBOUT(),
+            .CLKOUT0(),
+            .CLKOUT1(),
+            .CLKOUT2(),
+            .CLKOUT3(),
+            .CLKOUT4(),
+            .CLKOUT5(),
+            .DRDY(),
+            .LOCKED(),
+            .DO(),
+            .CLKFBIN(),
+            .CLKIN1(),
+            .CLKIN2(),
+            .CLKINSEL(),
+            .DCLK(),
+            .DEN(),
+            .DWE(),
+            .PWRDWN(),
+            .RST(),
+            .DI(),
+            .DADDR());
+''' % (site_name, CLKOUT1_DIVIDE, site_name))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()